Specification	CDCVF2510PW

Differential - Input:Output	False
Divider/Multiplier	False
Frequency - Max [Max]	175 MHz
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	0 °C
Output	LVTTL
Package / Case	24-TSSOP
Package / Case	0.173 in, 4.4 mm
PLL	Yes with Bypass
Ratio - Input:Output [custom]	2:11
Supplier Device Package	24-TSSOP
Type	PLL Clock Driver
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	3 V

CDCVF2510A Series

3.3-V phase-lock loop clock driver with 10 outputs for DRAM applications

Part	Operating Temperature [Max]	Mounting Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Supplier Device Package	PLL	Output	Ratio - Input:Output [custom]	Frequency - Max [Max]	Package / Case	Package / Case	Number of Circuits	Type
Texas Instruments CDCVF2510PW	85 °C	Surface Mount	3.6 V	3 V	24-TSSOP	Yes with Bypass	LVTTL	2:11	175 MHz	24-TSSOP	0.173 in 4.4 mm	1	PLL Clock Driver
Texas Instruments CDCVF2510PWG4	85 °C	Surface Mount	3.6 V	3 V	24-TSSOP	Yes with Bypass	LVTTL	2:11	175 MHz	24-TSSOP	0.173 in 4.4 mm	1	PLL Clock Driver
Texas Instruments CDCVF2510PWR	85 °C	Surface Mount	3.6 V	3 V	24-TSSOP	Yes with Bypass	LVTTL	2:11	175 MHz	24-TSSOP	0.173 in 4.4 mm	1	PLL Clock Driver
Texas Instruments CDCVF2510APWR	85 °C	Surface Mount	3.6 V	3 V	24-TSSOP	Yes with Bypass	LVTTL	2:11	175 MHz	24-TSSOP	0.173 in 4.4 mm	1	PLL Clock Driver

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	180	$ 6.28
Texas Instruments	TUBE	1	$ 6.42
		100	$ 5.24
		250	$ 4.12
		1000	$ 3.49

Description

General part information

CDCVF2510A Series

The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2510 operates at a 3.3-V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of 10 outputs provides 10 low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDCVF2510 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Documents

Technical documentation and resources

Datasheet

Generating Early Clock using TI's CDCVF2509/CDCVF2510 PLLs

Application note

3.3-V Phase-Lock Loop Clock Driver datasheet (Rev. C)

Data sheet