CDCVF2510APWR
Active175MHZ 10 TSSOP-24 CLOCK GENERATORS, PLLS, FREQUENCY SYNTHESIZERS ROHS
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CDCVF2510APWR
Active175MHZ 10 TSSOP-24 CLOCK GENERATORS, PLLS, FREQUENCY SYNTHESIZERS ROHS
Technical Specifications
Parameters and characteristics for this part
| Specification | CDCVF2510APWR |
|---|---|
| Differential - Input:Output | False |
| Divider/Multiplier | False |
| Frequency - Max [Max] | 175 MHz |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | 0 °C |
| Output | LVTTL |
| Package / Case | 24-TSSOP |
| Package / Case | 0.173 in, 4.4 mm |
| PLL | Yes with Bypass |
| Ratio - Input:Output [custom] | 2:11 |
| Supplier Device Package | 24-TSSOP |
| Type | PLL Clock Driver |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 2000 | $ 2.62 | |
| LCSC | Piece | 1 | $ 6.45 | |
| 200 | $ 2.50 | |||
| 500 | $ 2.41 | |||
| 1000 | $ 2.37 | |||
| Texas Instruments | LARGE T&R | 1 | $ 3.58 | |
| 100 | $ 2.92 | |||
| 250 | $ 2.30 | |||
| 1000 | $ 1.95 | |||
Description
General part information
CDCVF2510A Series
The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2510 operates at a 3.3-V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of 10 outputs provides 10 low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDCVF2510 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Documents
Technical documentation and resources
