The SY100EL29V is a dual differential register with differential data (inputs and outputs) and clock. The registers are triggered by a positive transition of the positive clock (CLK) input. A HIGH on the Reset (Rx) asynchronously resets the appropriate register so that the Q outputs go LOW. A HIGH on the Set (Sx) asynchronously resets the appropriate register so that the Q outputs go HIGH. The Set and Reset inputs cannot both be HIGH simultaneously. The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the devices. The clamping action will assert the /D and the /CLK sides of the inputs. The noninverting input will pull down to VEE and the inverting input will be biased around VCC/2. Because of the edge-triggered flip-flop nature of the devices, simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. The fully differential design of the devices makes them ideal for very high frequency applications where a registered data path is necessary.3.3V and 5V power supply option Differential D, CLK and Q Extended VEE range of –3.0V to –5.5V VBB output for single-ended use 1100MHz min. toggle frequency Asynchronous Reset and Set Available in 20-pin SOIC package