Integrated Circuits (ICs)

SN74LVC74AD

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DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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DocumentsSTANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices +26

Integrated Circuits (ICs)

SN74LVC74AD

Active

Texas Instruments

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

Deep-Dive with AI

DocumentsSTANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices +26

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74LVC74AD

Clock Frequency	150 MHz
Current - Output High, Low	24 mA
Current - Quiescent (Iq)	10 µA
Function	Reset, Set(Preset)
Input Capacitance	5 pF
Max Propagation Delay @ V, Max CL	5.2 ns
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-40 °C
Output Type	Complementary
Package / Case	14-SOIC
Package / Case [x]	0.154 in
Package / Case [y]	3.9 mm
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	1.65 V

SN74LVC74A-Q1 Series

Enhanced Product Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset

Part	Qualification	Function	Voltage - Supply [Max]	Voltage - Supply [Min]	Clock Frequency	Supplier Device Package	Current - Quiescent (Iq)	Mounting Type	Output Type	Number of Bits per Element	Max Propagation Delay @ V, Max CL	Grade	Package / Case [custom]	Package / Case [custom]	Package / Case	Trigger Type	Type	Input Capacitance	Number of Elements	Operating Temperature [Min]	Operating Temperature [Max]	Current - Output High, Low	Package / Case	Package / Case	Package / Case [x]	Package / Case [y]	Operating Temperature [Max]	Operating Temperature [Min]
Texas Instruments SN74LVC74AQPWRQ1	AEC-Q100	Reset Set(Preset)	3.6 V	2 V	150 MHz	14-TSSOP	10 µA	Surface Mount	Complementary	1	5.2 ns	Automotive	0.173 "	4.4 mm	14-TSSOP	Positive Edge	D-Type	5 pF	2	-40 °C	125 °C	24 mA
Texas Instruments SN74LVC74ABQAR		Reset Set(Preset)	3.6 V	1.65 V	100 MHz	14-WQFN (3x2.5)	10 µA	Surface Mount	Complementary	1	5.2 ns				14-WFQFN Exposed Pad	Positive Edge	D-Type	5 pF	2	-40 °C	125 °C	24 mA
Texas Instruments SN74LVC74ADBR		Reset Set(Preset)	3.6 V	1.65 V	150 MHz	14-SSOP	10 µA	Surface Mount	Complementary	1	5.2 ns				14-SSOP	Positive Edge	D-Type	5 pF	2	-40 °C	125 °C	24 mA	5.3 mm	0.209 "
Texas Instruments SN74LVC74APWG4		Reset Set(Preset)	3.6 V	1.65 V	150 MHz	14-TSSOP	10 µA	Surface Mount	Complementary	1	5.2 ns		0.173 "	4.4 mm	14-TSSOP	Positive Edge	D-Type	5 pF	2	-40 °C	125 °C	24 mA
Texas Instruments SN74LVC74ADT		Reset Set(Preset)	3.6 V	1.65 V	150 MHz		10 µA	Surface Mount	Complementary	1	5.2 ns				14-SOIC	Positive Edge	D-Type	5 pF	2	-40 °C	125 °C	24 mA			0.154 in	3.9 mm
Texas Instruments SN74LVC74ADRE4		Reset Set(Preset)	3.6 V	1.65 V	150 MHz		10 µA	Surface Mount	Complementary	1	5.2 ns				14-SOIC	Positive Edge	D-Type	5 pF	2	-40 °C	125 °C	24 mA			0.154 in	3.9 mm
Texas Instruments SN74LVC74AD		Reset Set(Preset)	3.6 V	1.65 V	150 MHz		10 µA	Surface Mount	Complementary	1	5.2 ns				14-SOIC	Positive Edge	D-Type	5 pF	2	-40 °C	125 °C	24 mA			0.154 in	3.9 mm
Texas Instruments SN74LVC74AMDREP		Reset Set(Preset)	3.6 V	2 V	100 MHz		10 µA	Surface Mount	Complementary	1	5.2 ns				14-SOIC	Positive Edge	D-Type	5 pF	2			24 mA			0.154 in	3.9 mm	125 °C	-55 °C
Texas Instruments SN74LVC74ADBRG4		Reset Set(Preset)	3.6 V	1.65 V	150 MHz	14-SSOP	10 µA	Surface Mount	Complementary	1	5.2 ns				14-SSOP	Positive Edge	D-Type	5 pF	2	-40 °C	125 °C	24 mA	5.3 mm	0.209 "
Texas Instruments SN74LVC74APWRE4		Reset Set(Preset)	3.6 V	1.65 V	150 MHz	14-TSSOP	10 µA	Surface Mount	Complementary	1	5.2 ns		0.173 "	4.4 mm	14-TSSOP	Positive Edge	D-Type	5 pF	2	-40 °C	125 °C	24 mA

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 1.02
		10	$ 0.91
		50	$ 0.86
		100	$ 0.71
		250	$ 0.66
		500	$ 0.59
		1000	$ 0.46
		2500	$ 0.43
		5000	$ 0.41
Texas Instruments	TUBE	1	$ 0.88
		100	$ 0.59
		250	$ 0.46
		1000	$ 0.30

Description

General part information

SN74LVC74A-Q1 Series

The SN74LVC74A dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCCoperation.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as a translator in a mixed 3.3 V/5 V system environment.

Documents

Technical documentation and resources

SN74LVC74AD

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SN74LVC74AD

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Technical Specifications

SN74LVC74A-Q1 Series

Pricing

Description

SN74LVC74A-Q1 Series

Documents

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Signal Switch Data Book (Rev. A)

Live Insertion

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset datasheet (Rev. W)

Input and Output Characteristics of Digital Integrated Circuits

Low-Voltage Logic (LVC) Designer's Guide

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

Design Summary for WCSP Little Logic (Rev. B)

Understanding Advanced Bus-Interface Products Design Guide

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

CMOS Power Consumption and CPD Calculation (Rev. B)

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Logic Guide (Rev. AB)

Power-Up Behavior of Clocked Devices (Rev. B)

Selecting the Right Level Translation Solution (Rev. A)

Implications of Slow or Floating CMOS Inputs (Rev. E)

Standard Linear & Logic for PCs, Servers & Motherboards

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Little Logic Guide 2018 (Rev. G)

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

LVC Characterization Information

How to Select Little Logic (Rev. A)

Texas Instruments Little Logic Application Report

LOGIC Pocket Data Book (Rev. B)

TI IBIS File Creation, Validation, and Distribution Processes

SN74LVC74A-Q1 Series