Integrated Circuits (ICs)

SN74LVC74APWG4

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Texas Instruments

IC FF D-TYPE DUAL 1BIT 14TSSOP

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Integrated Circuits (ICs)

SN74LVC74APWG4

Unknown

Texas Instruments

IC FF D-TYPE DUAL 1BIT 14TSSOP

Deep-Dive with AI

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74LVC74APWG4

Clock Frequency	150 MHz
Current - Output High, Low	24 mA
Current - Quiescent (Iq)	10 µA
Function	Reset, Set(Preset)
Input Capacitance	5 pF
Max Propagation Delay @ V, Max CL	5.2 ns
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-40 °C
Output Type	Complementary
Package / Case	14-TSSOP
Package / Case [custom]	0.173 "
Package / Case [custom]	4.4 mm
Supplier Device Package	14-TSSOP
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	1.65 V

SN74LVC74A-Q1 Series

Enhanced Product Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset

Part	Qualification	Function	Voltage - Supply [Max]	Voltage - Supply [Min]	Clock Frequency	Supplier Device Package	Current - Quiescent (Iq)	Mounting Type	Output Type	Number of Bits per Element	Max Propagation Delay @ V, Max CL	Grade	Package / Case [custom]	Package / Case [custom]	Package / Case	Trigger Type	Type	Input Capacitance	Number of Elements	Operating Temperature [Min]	Operating Temperature [Max]	Current - Output High, Low	Package / Case	Package / Case	Package / Case [x]	Package / Case [y]	Operating Temperature [Max]	Operating Temperature [Min]
Texas Instruments SN74LVC74AQPWRQ1	AEC-Q100	Reset Set(Preset)	3.6 V	2 V	150 MHz	14-TSSOP	10 µA	Surface Mount	Complementary	1	5.2 ns	Automotive	0.173 "	4.4 mm	14-TSSOP	Positive Edge	D-Type	5 pF	2	-40 °C	125 °C	24 mA
Texas Instruments SN74LVC74ABQAR		Reset Set(Preset)	3.6 V	1.65 V	100 MHz	14-WQFN (3x2.5)	10 µA	Surface Mount	Complementary	1	5.2 ns				14-WFQFN Exposed Pad	Positive Edge	D-Type	5 pF	2	-40 °C	125 °C	24 mA
Texas Instruments SN74LVC74ADBR		Reset Set(Preset)	3.6 V	1.65 V	150 MHz	14-SSOP	10 µA	Surface Mount	Complementary	1	5.2 ns				14-SSOP	Positive Edge	D-Type	5 pF	2	-40 °C	125 °C	24 mA	5.3 mm	0.209 "
Texas Instruments SN74LVC74APWG4		Reset Set(Preset)	3.6 V	1.65 V	150 MHz	14-TSSOP	10 µA	Surface Mount	Complementary	1	5.2 ns		0.173 "	4.4 mm	14-TSSOP	Positive Edge	D-Type	5 pF	2	-40 °C	125 °C	24 mA
Texas Instruments SN74LVC74ADT		Reset Set(Preset)	3.6 V	1.65 V	150 MHz		10 µA	Surface Mount	Complementary	1	5.2 ns				14-SOIC	Positive Edge	D-Type	5 pF	2	-40 °C	125 °C	24 mA			0.154 in	3.9 mm
Texas Instruments SN74LVC74ADRE4		Reset Set(Preset)	3.6 V	1.65 V	150 MHz		10 µA	Surface Mount	Complementary	1	5.2 ns				14-SOIC	Positive Edge	D-Type	5 pF	2	-40 °C	125 °C	24 mA			0.154 in	3.9 mm
Texas Instruments SN74LVC74AD		Reset Set(Preset)	3.6 V	1.65 V	150 MHz		10 µA	Surface Mount	Complementary	1	5.2 ns				14-SOIC	Positive Edge	D-Type	5 pF	2	-40 °C	125 °C	24 mA			0.154 in	3.9 mm
Texas Instruments SN74LVC74AMDREP		Reset Set(Preset)	3.6 V	2 V	100 MHz		10 µA	Surface Mount	Complementary	1	5.2 ns				14-SOIC	Positive Edge	D-Type	5 pF	2			24 mA			0.154 in	3.9 mm	125 °C	-55 °C
Texas Instruments SN74LVC74ADBRG4		Reset Set(Preset)	3.6 V	1.65 V	150 MHz	14-SSOP	10 µA	Surface Mount	Complementary	1	5.2 ns				14-SSOP	Positive Edge	D-Type	5 pF	2	-40 °C	125 °C	24 mA	5.3 mm	0.209 "
Texas Instruments SN74LVC74APWRE4		Reset Set(Preset)	3.6 V	1.65 V	150 MHz	14-TSSOP	10 µA	Surface Mount	Complementary	1	5.2 ns		0.173 "	4.4 mm	14-TSSOP	Positive Edge	D-Type	5 pF	2	-40 °C	125 °C	24 mA

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	900	$ 0.59

Description

General part information

SN74LVC74A-Q1 Series

The SN74LVC74A dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCCoperation.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as a translator in a mixed 3.3 V/5 V system environment.

Documents

Technical documentation and resources

No documents available