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CD4043BDWR

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Texas Instruments

CMOS QUAD NOR R/S LATCH WITH 3-STATE OUTPUTS

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SOIC (DW)
Integrated Circuits (ICs)

CD4043BDWR

Active
Texas Instruments

CMOS QUAD NOR R/S LATCH WITH 3-STATE OUTPUTS

Technical Specifications

Parameters and characteristics for this part

SpecificationCD4043BDWR
Circuit1:1
Current - Output High, Low [custom]6.8 mA
Current - Output High, Low [custom]6.8 mA
Delay Time - Propagation50 ns
Independent Circuits4
Logic TypeS-R Latch
Mounting TypeSurface Mount
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Output TypeTri-State
Package / Case16-SOIC
Package / Case [x]0.295 in
Package / Case [y]7.5 mm
Supplier Device Package16-SOIC
Voltage - Supply [Max]18 V
Voltage - Supply [Min]3 V

CD4043B Series

CMOS Quad NOR R/S Latch with 3-State Outputs

PartOutput TypeSupplier Device PackageIndependent CircuitsCircuitLogic TypeDelay Time - PropagationPackage / CasePackage / Case [x]Package / Case [y]Operating Temperature [Min]Operating Temperature [Max]Mounting TypeVoltage - Supply [Max]Voltage - Supply [Min]Current - Output High, Low [custom]Current - Output High, Low [custom]Package / CasePackage / Case
16 SOIC
Texas Instruments
Tri-State
16-SOIC
4
1:1
S-R Latch
50 ns
16-SOIC
0.154 in
3.9 mm
-55 °C
125 °C
Surface Mount
18 V
3 V
6.8 mA
6.8 mA
PDIP (N)
Texas Instruments
Tri-State
16-PDIP
4
1:1
S-R Latch
50 ns
16-DIP
-55 °C
125 °C
Through Hole
18 V
3 V
6.8 mA
6.8 mA
0.3 in
7.62 mm
SOIC (DW)
Texas Instruments
Tri-State
16-SOIC
4
1:1
S-R Latch
50 ns
16-SOIC
0.295 in
7.5 mm
-55 °C
125 °C
Surface Mount
18 V
3 V
6.8 mA
6.8 mA
16-TSSOP
Texas Instruments
Tri-State
16-TSSOP
4
1:1
S-R Latch
50 ns
16-TSSOP
0.173 in
4.4 mm
-55 °C
125 °C
Surface Mount
18 V
3 V
6.8 mA
6.8 mA
16-TSSOP
Texas Instruments
Tri-State
16-TSSOP
4
1:1
S-R Latch
50 ns
16-TSSOP
0.173 in
4.4 mm
-55 °C
125 °C
Surface Mount
18 V
3 V
6.8 mA
6.8 mA
16 SOIC
Texas Instruments
Tri-State
16-SOIC
4
1:1
S-R Latch
50 ns
16-SOIC
0.154 in
3.9 mm
-55 °C
125 °C
Surface Mount
18 V
3 V
6.8 mA
6.8 mA
Texas Instruments-LM5026MT/NOPB PWM and Resonant Controllers Current Mode PWM Controller 3A 590kHz 16-Pin TSSOP Tube
Texas Instruments
Tri-State
16-TSSOP
4
1:1
S-R Latch
50 ns
16-TSSOP
0.173 in
4.4 mm
-55 °C
125 °C
Surface Mount
18 V
3 V
6.8 mA
6.8 mA
SOIC (D)
Texas Instruments
Tri-State
16-SOIC
4
1:1
S-R Latch
50 ns
16-SOIC
0.154 in
3.9 mm
-55 °C
125 °C
Surface Mount
18 V
3 V
6.8 mA
6.8 mA

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 0.76
10$ 0.67
25$ 0.63
100$ 0.51
250$ 0.48
500$ 0.41
1000$ 0.32
Digi-Reel® 1$ 0.76
10$ 0.67
25$ 0.63
100$ 0.51
250$ 0.48
500$ 0.41
1000$ 0.32
Tape & Reel (TR) 2000$ 0.29
6000$ 0.27
10000$ 0.26
Texas InstrumentsLARGE T&R 1$ 0.50
100$ 0.38
250$ 0.28
1000$ 0.20

Description

General part information

CD4043B Series

CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.

The CD4043B and CD4044B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline package (D, DR, DT, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.