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VQFN / 64
Integrated Circuits (ICs)

ATMEGA128-16MU

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Microchip Technology

8 BIT MCU, LOW POWER HIGH PERFORMANCE, AVR ATMEGA FAMILY ATMEGA128 SERIES MICROCONTROLLERS, AVR

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VQFN / 64
Integrated Circuits (ICs)

ATMEGA128-16MU

Active
Microchip Technology

8 BIT MCU, LOW POWER HIGH PERFORMANCE, AVR ATMEGA FAMILY ATMEGA128 SERIES MICROCONTROLLERS, AVR

Technical Specifications

Parameters and characteristics for this part

SpecificationATMEGA128-16MU
ConnectivityEBI/EMI, UART/USART, I2C, SPI
Core ProcessorAVR
Core Size8-Bit
Data Converters [custom]8
Data Converters [custom]10
EEPROM Size4K x 8
Mounting TypeSurface Mount
Number of I/O53
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Oscillator TypeInternal
Package / Case64-VFQFN Exposed Pad
Program Memory TypeFLASH
RAM Size4K x 8
Speed16 MHz
Supplier Device Package64-QFN (9x9)
Voltage - Supply (Vcc/Vdd) [Max]5.5 V
Voltage - Supply (Vcc/Vdd) [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTray 1$ 15.01
25$ 13.77
100$ 13.24
Microchip DirectTRAY 1$ 15.01
25$ 13.77
100$ 12.45
1000$ 11.46
5000$ 10.91
NewarkEach 100$ 13.77

Description

General part information

ATmega128RFA1 Series

The high-performance, low-power Microchip 8-bit AVR® RISC-based microcontroller combines 128 KB flash memory with read-while-write capabilities, 4 KB EEPROM, 4 KB SRAM, 53 general purpose I/O lines, 32 general purpose working registers, a real-time counter, four flexible timer/counters with compare modes and PWM, two USARTs, a byte-oriented Two-Wire serial interface, an 8-channel/10-bit A/D converter with optional differential input stage with programmable gain, programmable watchdog timer with internal oscillator, SPI serial port, a JTAG (IEEE® 1149.1 compliant) test interface for accessing the on-chip debugging and programming, and six software selectable power saving modes. The device operates between 2.7-5.5 volts.

By executing powerful instructions in a single clock cycle, the device achieves throughputs approaching one MIPS per MHz, balancing power consumption and processing speed.