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8-LSSOP
Integrated Circuits (ICs)

SN74LVC2G74DCT3

Active
Texas Instruments

1.65V~5.5V D-TYPE 140MHZ 10UA 6.1NS@5V,50PF SSOP-8-2.8MM FLIP FLOPS ROHS

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8-LSSOP
Integrated Circuits (ICs)

SN74LVC2G74DCT3

Active
Texas Instruments

1.65V~5.5V D-TYPE 140MHZ 10UA 6.1NS@5V,50PF SSOP-8-2.8MM FLIP FLOPS ROHS

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LVC2G74DCT3
Clock Frequency140 MHz
Current - Output High, Low [x]32 mA
Current - Output High, Low [y]32 mA
Current - Quiescent (Iq)10 µA
FunctionReset, Set(Preset)
Input Capacitance5 pF
Max Propagation Delay @ V, Max CL6.1 ns
Mounting TypeSurface Mount
Number of Bits per Element1
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Output TypeComplementary
Supplier Device PackageSM8
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]1.65 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 0.76
10$ 0.67
25$ 0.63
100$ 0.51
250$ 0.48
500$ 0.41
1000$ 0.32
Digi-ReelÛ 1$ 0.76
10$ 0.67
25$ 0.63
100$ 0.51
250$ 0.48
500$ 0.41
1000$ 0.32
Tape & Reel (TR) 3000$ 0.25
LCSCPiece 5$ 0.29
50$ 0.23
150$ 0.20
500$ 0.17
3000$ 0.15
6000$ 0.14
Texas InstrumentsLARGE T&R 1$ 0.28
100$ 0.19
250$ 0.15
1000$ 0.10

Description

General part information

SN74LVC2G74 Series

This single positive-edge-triggered D-type flip-flop is designed for 1.65 V to 5.5 V VCCoperation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.