Integrated Circuits (ICs)

SN74LVC2G74YEPR

Obsolete

Texas Instruments

IC FF D-TYPE SNGL 1BIT 8DSBGA

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Integrated Circuits (ICs)

SN74LVC2G74YEPR

Obsolete

Texas Instruments

IC FF D-TYPE SNGL 1BIT 8DSBGA

Deep-Dive with AI

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74LVC2G74YEPR

Clock Frequency	140 MHz
Current - Output High, Low [x]	32 mA
Current - Output High, Low [y]	32 mA
Current - Quiescent (Iq)	10 µA
Function	Reset, Set(Preset)
Input Capacitance	5 pF
Max Propagation Delay @ V, Max CL	5.4 ns
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Complementary
Package / Case	8-XFBGA, DSBGA
Supplier Device Package	8-DSBGA (1.9x0.9)
Supplier Device Package [x]	1.9
Supplier Device Package [y]	0.9
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	1.65 V

SN74LVC2G74 Series

Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

Part	Max Propagation Delay @ V, Max CL	Current - Output High, Low [y]	Current - Output High, Low [x]	Function	Number of Bits per Element	Operating Temperature [Max]	Operating Temperature [Min]	Current - Quiescent (Iq)	Output Type	Input Capacitance	Trigger Type	Number of Elements	Clock Frequency	Voltage - Supply [Max]	Voltage - Supply [Min]	Package / Case	Supplier Device Package	Mounting Type	Type	Supplier Device Package [y]	Supplier Device Package [x]	Package / Case [y]	Package / Case [y]
Texas Instruments SN74LVC2G74YZPR	5.4 ns	32 mA	32 mA	Reset Set(Preset)	1	85 °C	-40 °C	10 µA	Complementary	5 pF	Positive Edge	1	140 MHz	5.5 V	1.65 V	8-XFBGA DSBGA	8-DSBGA	Surface Mount	D-Type
Texas Instruments SN74LVC2G74YZAR	5.4 ns	32 mA	32 mA	Reset Set(Preset)	1	85 °C	-40 °C	10 µA	Complementary	5 pF	Positive Edge	1	140 MHz	5.5 V	1.65 V	8-XFBGA DSBGA	8-DSBGA (1.9x0.9)	Surface Mount	D-Type	0.9	1.9
Texas Instruments SN74LVC2G74DCT3	6.1 ns	32 mA	32 mA	Reset Set(Preset)	1	125 °C	-40 °C	10 µA	Complementary	5 pF	Positive Edge	1	140 MHz	5.5 V	1.65 V		SM8	Surface Mount	D-Type
Texas Instruments SN74LVC2G74YEAR	5.4 ns	32 mA	32 mA	Reset Set(Preset)	1	85 °C	-40 °C	10 µA	Complementary	5 pF	Positive Edge	1	140 MHz	5.5 V	1.65 V	8-XFBGA DSBGA	8-XFBGA DSBGA	Surface Mount	D-Type
Texas Instruments SN74LVC2G74DCUR	4.4 ns	32 mA	32 mA	Reset Set(Preset)	1	125 °C	-40 °C	10 µA	Complementary	5 pF	Positive Edge	1	200 MHz	5.5 V	1.65 V	8-VFSOP		Surface Mount	D-Type			2.3 mm	0.091 in
Texas Instruments SN74LVC2G74DCURE4	5.1 ns	32 mA	32 mA	Reset Set(Preset)	1	125 °C	-40 °C	10 µA	Complementary	5 pF	Positive Edge	1	140 MHz	5.5 V	1.65 V	8-VFSOP		Surface Mount	D-Type			2.3 mm	0.091 in
Texas Instruments SN74LVC2G74DCUTE4	5.1 ns	32 mA	32 mA	Reset Set(Preset)	1	125 °C	-40 °C	10 µA	Complementary	5 pF	Positive Edge	1	140 MHz	5.5 V	1.65 V	8-VFSOP		Surface Mount	D-Type			2.3 mm	0.091 in
Texas Instruments SN74LVC2G74DCURG4	4.4 ns	32 mA	32 mA	Reset Set(Preset)	1	125 °C	-40 °C	10 µA	Complementary	5 pF	Positive Edge	1	200 MHz	5.5 V	1.65 V	8-VFSOP		Surface Mount	D-Type			2.3 mm	0.091 in
Texas Instruments SN74LVC2G74YEPR	5.4 ns	32 mA	32 mA	Reset Set(Preset)	1	85 °C	-40 °C	10 µA	Complementary	5 pF	Positive Edge	1	140 MHz	5.5 V	1.65 V	8-XFBGA DSBGA	8-DSBGA (1.9x0.9)	Surface Mount	D-Type	0.9	1.9

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Description

General part information

SN74LVC2G74 Series

This single positive-edge-triggered D-type flip-flop is designed for 1.65 V to 5.5 V VCCoperation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

Documents

Technical documentation and resources

No documents available