Integrated Circuits (ICs)

SN74LVTH574ZQNR

Obsolete

Texas Instruments

IC FF D-TYPE SNGL 8BIT 20BGA

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Integrated Circuits (ICs)

SN74LVTH574ZQNR

Obsolete

Texas Instruments

IC FF D-TYPE SNGL 8BIT 20BGA

Deep-Dive with AI

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74LVTH574ZQNR

Clock Frequency	150 MHz
Current - Output High, Low [custom]	64 mA
Current - Output High, Low [custom]	32 mA
Current - Quiescent (Iq)	190 çA
Function	Standard
Input Capacitance	3 pF
Max Propagation Delay @ V, Max CL	4.5 ns
Mounting Type	Surface Mount
Number of Bits per Element	8
Number of Elements	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State, Non-Inverted
Package / Case	20-VFBGA
Supplier Device Package	20-BGA MICROSTAR JUNIOR (4x3)
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	2.7 V

SN74LVTH574-EP Series

Enhanced Product 3.3-V Abt Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs

Part	Max Propagation Delay @ V, Max CL	Output Type	Number of Elements	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]	Trigger Type	Current - Quiescent (Iq)	Supplier Device Package	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Function	Input Capacitance	Package / Case [y]	Package / Case	Package / Case [x]	Clock Frequency	Voltage - Supply [Min]	Voltage - Supply [Max]	Number of Bits per Element	Type	Package / Case [y]	Package / Case	Package / Case
Texas Instruments SN74LVTH574IPWREP	4.5 ns	Non-Inverted Tri-State	1	Surface Mount	85 °C	-40 °C	Positive Edge	190 çA	20-TSSOP	64 mA	32 mA	Standard	3 pF	4.4 mm	20-TSSOP	0.173 in	150 MHz	2.7 V	3.6 V	8	D-Type
Texas Instruments SN74LVTH574DBR	4.5 ns	Non-Inverted Tri-State	1	Surface Mount	85 °C	-40 °C	Positive Edge	190 çA	20-SSOP	64 mA	32 mA	Standard	3 pF		20-SSOP		150 MHz	2.7 V	3.6 V	8	D-Type
Texas Instruments SN74LVTH574DB	4.5 ns	Non-Inverted Tri-State	1	Surface Mount	85 °C	-40 °C	Positive Edge	190 çA	20-SSOP	64 mA	32 mA	Standard	3 pF		20-SSOP		150 MHz	2.7 V	3.6 V	8	D-Type
Texas Instruments SN74LVTH574DWR	4.5 ns	Non-Inverted Tri-State	1	Surface Mount	85 °C	-40 °C	Positive Edge	190 çA	20-SOIC	64 mA	32 mA	Standard	3 pF	0.295 in	20-SOIC		150 MHz	2.7 V	3.6 V	8	D-Type	7.5 mm
Texas Instruments SN74LVTH574ZQNR	4.5 ns	Non-Inverted Tri-State	1	Surface Mount	85 °C	-40 °C	Positive Edge	190 çA	20-BGA MICROSTAR JUNIOR (4x3)	64 mA	32 mA	Standard	3 pF		20-VFBGA		150 MHz	2.7 V	3.6 V	8	D-Type
Texas Instruments SN74LVTH574PWR	4.5 ns	Non-Inverted Tri-State	1	Surface Mount	85 °C	-40 °C	Positive Edge	190 çA	20-TSSOP	64 mA	32 mA	Standard	3 pF	4.4 mm	20-TSSOP	0.173 in	150 MHz	2.7 V	3.6 V	8	D-Type
Texas Instruments SN74LVTH574DW	4.5 ns	Non-Inverted Tri-State	1	Surface Mount	85 °C	-40 °C	Positive Edge	190 çA	20-SOIC	64 mA	32 mA	Standard	3 pF	0.295 in	20-SOIC		150 MHz	2.7 V	3.6 V	8	D-Type	7.5 mm
Texas Instruments SN74LVTH574PW	4.5 ns	Non-Inverted Tri-State	1	Surface Mount	85 °C	-40 °C	Positive Edge	190 çA	20-TSSOP	64 mA	32 mA	Standard	3 pF	4.4 mm	20-TSSOP	0.173 in	150 MHz	2.7 V	3.6 V	8	D-Type
Texas Instruments SN74LVTH574PWRG4	4.5 ns	Non-Inverted Tri-State	1	Surface Mount	85 °C	-40 °C	Positive Edge	190 çA	20-TSSOP	64 mA	32 mA	Standard	3 pF	4.4 mm	20-TSSOP	0.173 in	150 MHz	2.7 V	3.6 V	8	D-Type
Texas Instruments SN74LVTH574NSR	4.5 ns	Non-Inverted Tri-State	1	Surface Mount	85 °C	-40 °C	Positive Edge	190 çA	20-SO	64 mA	32 mA	Standard	3 pF		20-SOIC		150 MHz	2.7 V	3.6 V	8	D-Type		0.209 "	5.3 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Bulk	437	$ 0.69

Description

General part information

SN74LVTH574-EP Series

These octal flip-flops are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.

The eight flip-flops of the ’LVTH574 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

Documents

Technical documentation and resources

No documents available