
SN74AHC125N
Active1 8MA 2V~5.5V 8MA 4 PDIP-14 BUFFERS, DRIVERS, RECEIVERS, TRANSCEIVERS ROHS
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SN74AHC125N
Active1 8MA 2V~5.5V 8MA 4 PDIP-14 BUFFERS, DRIVERS, RECEIVERS, TRANSCEIVERS ROHS
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74AHC125N |
|---|---|
| Current - Output High, Low [custom] | 8 mA |
| Current - Output High, Low [custom] | 8 mA |
| Logic Type | Buffer, Non-Inverting |
| Mounting Type | Through Hole |
| Number of Bits per Element | 1 |
| Number of Elements | 4 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | 3-State |
| Package / Case | 14-DIP |
| Package / Case [x] | 0.3 " |
| Package / Case [y] | 7.62 mm |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 0.73 | |
| 10 | $ 0.65 | |||
| 25 | $ 0.61 | |||
| 100 | $ 0.50 | |||
| 250 | $ 0.46 | |||
| 500 | $ 0.39 | |||
| 1000 | $ 0.31 | |||
| 2500 | $ 0.28 | |||
| 5000 | $ 0.26 | |||
| LCSC | Piece | 1 | $ 0.20 | |
| 200 | $ 0.08 | |||
| 500 | $ 0.07 | |||
| 1000 | $ 0.07 | |||
| Texas Instruments | TUBE | 1 | $ 0.68 | |
| 100 | $ 0.46 | |||
| 250 | $ 0.35 | |||
| 1000 | $ 0.24 | |||
Description
General part information
SN74AHC125-EP Series
The SNx4AHC125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable ( OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output.
To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SNx4AHC125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable ( OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output.
Documents
Technical documentation and resources