AD5343BRUZ-REEL
Active+2.5V TO 5.5V, 230ΜA DUAL RAIL-TO-RAIL VOLTAGE OUTPUT 12-BIT DAC WITH BYTE-LOAD PARALLEL INTERFACE IN 20-LEAD TSSOP
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AD5343BRUZ-REEL
Active+2.5V TO 5.5V, 230ΜA DUAL RAIL-TO-RAIL VOLTAGE OUTPUT 12-BIT DAC WITH BYTE-LOAD PARALLEL INTERFACE IN 20-LEAD TSSOP
Technical Specifications
Parameters and characteristics for this part
| Specification | AD5343BRUZ-REEL |
|---|---|
| Architecture | String DAC |
| Data Interface | Parallel |
| Differential Output | No |
| DNL (LSB) Tolerance | 0.2 LSB |
| INL (LSB) Tolerance | 2 LSB |
| Mounting Type | Surface Mount |
| Number of Bits | 12 bits |
| Number of D/A Converters | 2 count |
| Operating Temperature (Max) | 105 °C |
| Operating Temperature (Min) | -40 °C |
| Output Type | Voltage - Buffered |
| Package Length | 0.173 in |
| Package Name | 20-TSSOP |
| Package Width | 4.4 mm |
| Reference Type | External |
| Settling Time | 10 µs |
| Voltage - Supply, Analog (Max) | 5.5 V |
| Voltage - Supply, Analog (Min) | 2.5 V |
| Voltage - Supply, Digital (Max) | 5.5 V |
| Voltage - Supply, Digital (Min) | 2.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | Updated |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 2500 | $ 10.74 | <1d |
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Description
General part information
AD5343 Series
TheAD5332/AD5333/AD5342/ AD5343 are dual 8-,10-,and 12-bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 230 µA at 3 V, and feature a power-down pin, PD that further reduces the current to 80 nA. These devices incorporate an on-chip output buffer that can drive the output to both supply rails, while the AD5333 and AD5342 allow a choice of buffered or unbuffered reference input.PRODUCT HIGHLIGHTSAvailable in a 20-lead TSSOP packageLow power, single supply operation from 2.5 V to 5.5 V supplyConsumes 0.69 mW at 3 V and 1.5 mW at 5 VOn-chip output buffer can drive output to both supply rails8-Bit Parallel interface for upper and lower byte load (controlled via HBEN pin)
Documents
Technical documentation and resources
