Texas Instruments

This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCCoperation. One device per DIMM is required to drive up to 18 stacked SDRAM loads or two devices per DIMM are required to drive up to 36 stacked SDRAM loads. All inputs are SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (QERR) output. The 74SSTUB32868A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The 74SSTUB32868A accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs (D1-D5, D7, D9-D12, D17-D28 when C = 0; or D1-D12, D17-D20, D22, D24-D28 when C = 1) and indicates whether a parity error has occurred on the open-drainQERRpin (active low). The convention is even parity; that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all DIMM-independent D-inputs must be tied to a known logic state. The 74SSTUB32868A includes a parity checking function. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of the device. Two clock cycles after the data are registered, the corresponding QERR signal is generated. If an error occurs and theQERRoutput is driven low, it stays latched low for a minimum of two clock cycles or untilRESETis driven low. If two or more consecutive parity errors occur, theQERRoutput is driven low and latched low for a clock duration equal to the parity error duration or untilRESETis driven low. If a parity error occurs on the clock cycle before the device enters the low-power mode (LPM) and theQERRoutput is driven low, it stays latched low for the LPM duration plus two clock cycles or untilRESETis driven low. The DIMM-dependent signals (DCKE0, DCKE1, DODT0, DODT1,DCS0andDCS1) are not included in the parity check computation. The C input controls the pinout configuration from register-A configuration (when low) to register-B configuration (when high). The C input should not be switched during normal operation. It should be hard-wired to a valid low or high level to configure the register in the desired mode. In the DDR2 RDIMM application,RESETis specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is cleared and the data outputs is driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register becomes active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition ofRESETuntil the input receivers are fully enabled, the design of the 74SSTUB32868A must ensure that the outputs remain low, thus ensuring no glitches on the output. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. The device supports low-power standby operation. WhenRESETis low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, whenRESETis low, all registers are reset and all outputs are forced low exceptQERR. The LVCMOS RESET and C inputs always must be held at a valid logic high or low level. The device also supports low-power active operation by monitoring both system chip select (DCS0andDCS1) and CSGEN inputs and will gate the Qn outputs from changing states when CSGEN,DCS0, andDCS1inputs are high. If CSGEN,DCS0orDCS1input is low, the Qn outputs function normally. Also, if bothDCS0andDCS1inputs are high, the device will gate theQERRoutput from changing states. If eitherDCS0orDCS1is low, theQERRoutput functions normally. TheRESETinput has priority over theDCS0andDCS1control and when driven low forces the Qn outputs low, and theQERRoutput high. If the chip-select control functionality is not desired, then the CSGEN input can be hard-wired to ground, in which case, the setup-time requirement forDCS0andDCS1would be the same as for the other D data inputs. To control the low-power mode withDCS0andDCS1only, then the CSGEN input should be pulled up to VCCthrough a pullup resistor. The two VREFpins (A5 and AB5) are connected together internally by approximately 150. However, it is necessary to connect only one of the two VREFpins to the external VREFpower supply. An unused VREFpin should be terminated with a VREFcoupling capacitor. This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCCoperation. One device per DIMM is required to drive up to 18 stacked SDRAM loads or two devices per DIMM are required to drive up to 36 stacked SDRAM loads. All inputs are SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (QERR) output. The 74SSTUB32868A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The 74SSTUB32868A accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs (D1-D5, D7, D9-D12, D17-D28 when C = 0; or D1-D12, D17-D20, D22, D24-D28 when C = 1) and indicates whether a parity error has occurred on the open-drainQERRpin (active low). The convention is even parity; that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all DIMM-independent D-inputs must be tied to a known logic state. The 74SSTUB32868A includes a parity checking function. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of the device. Two clock cycles after the data are registered, the corresponding QERR signal is generated. If an error occurs and theQERRoutput is driven low, it stays latched low for a minimum of two clock cycles or untilRESETis driven low. If two or more consecutive parity errors occur, theQERRoutput is driven low and latched low for a clock duration equal to the parity error duration or untilRESETis driven low. If a parity error occurs on the clock cycle before the device enters the low-power mode (LPM) and theQERRoutput is driven low, it stays latched low for the LPM duration plus two clock cycles or untilRESETis driven low. The DIMM-dependent signals (DCKE0, DCKE1, DODT0, DODT1,DCS0andDCS1) are not included in the parity check computation. The C input controls the pinout configuration from register-A configuration (when low) to register-B configuration (when high). The C input should not be switched during normal operation. It should be hard-wired to a valid low or high level to configure the register in the desired mode. In the DDR2 RDIMM application,RESETis specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is cleared and the data outputs is driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register becomes active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition ofRESETuntil the input receivers are fully enabled, the design of the 74SSTUB32868A must ensure that the outputs remain low, thus ensuring no glitches on the output. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. The device supports low-power standby operation. WhenRESETis low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, whenRESETis low, all registers are reset and all outputs are forced low exceptQERR. The LVCMOS RESET and C inputs always must be held at a valid logic high or low level. The device also supports low-power active operation by monitoring both system chip select (DCS0andDCS1) and CSGEN inputs and will gate the Qn outputs from changing states when CSGEN,DCS0, andDCS1inputs are high. If CSGEN,DCS0orDCS1input is low, the Qn outputs function normally. Also, if bothDCS0andDCS1inputs are high, the device will gate theQERRoutput from changing states. If eitherDCS0orDCS1is low, theQERRoutput functions normally. TheRESETinput has priority over theDCS0andDCS1control and when driven low forces the Qn outputs low, and theQERRoutput high. If the chip-select control functionality is not desired, then the CSGEN input can be hard-wired to ground, in which case, the setup-time requirement forDCS0andDCS1would be the same as for the other D data inputs. To control the low-power mode withDCS0andDCS1only, then the CSGEN input should be pulled up to VCCthrough a pullup resistor. The two VREFpins (A5 and AB5) are connected together internally by approximately 150. However, it is necessary to connect only one of the two VREFpins to the external VREFpower supply. An unused VREFpin should be terminated with a VREFcoupling capacitor.