| Signal Switches, Multiplexers, Decoders | 3 | Active | |
| Signal Switches, Multiplexers, Decoders | 1 | Active | |
| Flip Flops | 3 | Active | |
| Integrated Circuits (ICs) | 1 | Active | |
| Shift Registers | 1 | Active | |
74AC112Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset | Logic | 3 | Active | The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.
The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. |
| Logic | 11 | Active | |
| Logic | 7 | Active | |
| Buffers, Drivers, Receivers, Transceivers | 3 | Active | This octal bus transceiver is designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
The device allows noninverted data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enableinput can be used to disable the device so that the buses are effectively isolated.
The 74AC11245 is characterized for operation from -40°C to 85°C.
This octal bus transceiver is designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
The device allows noninverted data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enableinput can be used to disable the device so that the buses are effectively isolated.
The 74AC11245 is characterized for operation from -40°C to 85°C. |
| Signal Switches, Multiplexers, Decoders | 7 | Active | |
