CD74HCT173High Speed CMOS Logic Quad D-Type Flip-Flops with 3-State Outputs | Integrated Circuits (ICs) | 2 | Obsolete | High Speed CMOS Logic Quad D-Type Flip-Flops with 3-State Outputs |
CD74HCT174High Speed CMOS Logic Hex D-Type Flip-Flop with Reset | Integrated Circuits (ICs) | 4 | Active | The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR\ input, when low, sets all outputs to a low state.
Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin compatible to the ’LS174.
The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR\ input, when low, sets all outputs to a low state.
Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin compatible to the ’LS174. |
CD74HCT175High Speed CMOS Logic Quad D-Type Flip-Flop with Reset | Logic | 3 | Active | The ’HC175 and ’HCT175 are high speed Quad D-type Flip-Flops with individual D-inputs and Q, Q\ complementary outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices.
Information at the D input is transferred to the Q, Q\ outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a common reset (MR\). Resetting is accomplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four Q\ outputs to a logic 1.
The ’HC175 and ’HCT175 are high speed Quad D-type Flip-Flops with individual D-inputs and Q, Q\ complementary outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices.
Information at the D input is transferred to the Q, Q\ outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a common reset (MR\). Resetting is accomplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four Q\ outputs to a logic 1. |
CD74HCT191High Speed CMOS Logic Presettable Synchronous 4-Bit Binary Up/Down Counters | Counters, Dividers | 2 | Active | The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters.
Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\ input. Counting occurs when LOAD\ is high, count enable (CTEN)\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock.
When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ (see Figure 2).
If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3).
The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters.
Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\ input. Counting occurs when LOAD\ is high, count enable (CTEN)\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock.
When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ (see Figure 2).
If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3). |
CD74HCT202-ch, 4-input, 4.5-V to 5.5-V NAND gates with TTL-compatible CMOS inputs | Integrated Circuits (ICs) | 3 | Active | This device contains two independent 4-input NAND gates. Each gate performs the Boolean function Y =A ● B ● C ● Din positive logic.
This device contains two independent 4-input NAND gates. Each gate performs the Boolean function Y =A ● B ● C ● Din positive logic. |
CD74HCT212-ch 4-input 4.5-V to 5.5-V AND gate with TTL-compatible inputs | Gates and Inverters | 3 | Active | This device contains two independent 4-input AND gates. Each gate performs the Boolean function Y = A ● B ● C ● D in positive logic.
This device contains two independent 4-input AND gates. Each gate performs the Boolean function Y = A ● B ● C ● D in positive logic. |
CD74HCT221High Speed CMOS Logic Dual Monostable Multivibrators with Reset | Logic | 6 | Active | The ’HC221 and CD74HCT221 are dual monostable multivibrators with reset. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of RXand CXprovides a wide range of output pulse widths from the Q and Q\ terminals. Pulse triggering on the B input occurs at a particular voltage level and is not related to the rise and fall time of the trigger pulse.
Once triggered, the outputs are independent of further trigger inputs on A\ and B. The output pulse can be terminated by a LOW level on the Reset (R)\ pin. Trailing Edge triggering (A)\ and leading-edge-triggering (B) inputs are provided for triggering from either edge of the input pulse. On power up, the IC is reset. If either Mono is not used each input (on the unused device) must be terminated either high or low.
The minimum value of external resistance, RX, is typically 500. The minimum value of external capacitance, CX, is 0pF. The calculation for the pulse width is tW= 0.7 RXCXat VCC= 4.5V.
The ’HC221 and CD74HCT221 are dual monostable multivibrators with reset. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of RXand CXprovides a wide range of output pulse widths from the Q and Q\ terminals. Pulse triggering on the B input occurs at a particular voltage level and is not related to the rise and fall time of the trigger pulse.
Once triggered, the outputs are independent of further trigger inputs on A\ and B. The output pulse can be terminated by a LOW level on the Reset (R)\ pin. Trailing Edge triggering (A)\ and leading-edge-triggering (B) inputs are provided for triggering from either edge of the input pulse. On power up, the IC is reset. If either Mono is not used each input (on the unused device) must be terminated either high or low.
The minimum value of external resistance, RX, is typically 500. The minimum value of external capacitance, CX, is 0pF. The calculation for the pulse width is tW= 0.7 RXCXat VCC= 4.5V. |
CD74HCT238High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer Inverting and Non-Inverting | Logic | 5 | Active | High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer Inverting and Non-Inverting |
CD74HCT243High Speed CMOS Logic Quad-Bus Transceiver with 3-State Outputs | Integrated Circuits (ICs) | 4 | Active | High Speed CMOS Logic Quad-Bus Transceiver with 3-State Outputs |
CD74HCT251High Speed CMOS Logic 8-Input Multiplexer, 3-State | Logic | 4 | Active | High Speed CMOS Logic 8-Input Multiplexer, 3-State |
