Texas Instruments

The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The two modes of operation, shift right (Q0-Q1) and parallel load, are controlled by the state of the Parallel Enable (PE)\ input. Serial data enters the first flip-flop (Q0) via the J and K\ inputs when the PE\ input is high, and is shifted one bit in the direction Q0-Q1-Q2-Q3following each Low to High clock transition. The J and K\ inputs provide the flexibility of the JK-type input for special applications and by tying the two pins together, the simple D-type input for general applications. The device appears as four common-clocked D flip-flops when the PE\ input is Low. After the Low to High clock transition, data on the parallel inputs (D0-D3) is transferred to the respective Q0-Q3outputs. Shift left operation (Q3-Q2) can be achieved by tying the Qnoutputs to the Dn-1 inputs and holding the PE\ input low. All parallel and serial data transfers are synchronous, occurring after each Low to High clock transition. The ’HC195 series utilizes edge triggering; therefore, there is no restriction on the activity of the J, K\, Pn and PE\ inputs for logic operations, other than set-up and hold time requirements. A Low on the asynchronous Master Reset (MR)\ input sets all Q outputs Low, independent of any other input condition. The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The two modes of operation, shift right (Q0-Q1) and parallel load, are controlled by the state of the Parallel Enable (PE)\ input. Serial data enters the first flip-flop (Q0) via the J and K\ inputs when the PE\ input is high, and is shifted one bit in the direction Q0-Q1-Q2-Q3following each Low to High clock transition. The J and K\ inputs provide the flexibility of the JK-type input for special applications and by tying the two pins together, the simple D-type input for general applications. The device appears as four common-clocked D flip-flops when the PE\ input is Low. After the Low to High clock transition, data on the parallel inputs (D0-D3) is transferred to the respective Q0-Q3outputs. Shift left operation (Q3-Q2) can be achieved by tying the Qnoutputs to the Dn-1 inputs and holding the PE\ input low. All parallel and serial data transfers are synchronous, occurring after each Low to High clock transition. The ’HC195 series utilizes edge triggering; therefore, there is no restriction on the activity of the J, K\, Pn and PE\ inputs for logic operations, other than set-up and hold time requirements. A Low on the asynchronous Master Reset (MR)\ input sets all Q outputs Low, independent of any other input condition.

The ’HC221 and CD74HCT221 are dual monostable multivibrators with reset. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of RXand CXprovides a wide range of output pulse widths from the Q and Q\ terminals. Pulse triggering on the B input occurs at a particular voltage level and is not related to the rise and fall time of the trigger pulse. Once triggered, the outputs are independent of further trigger inputs on A\ and B. The output pulse can be terminated by a LOW level on the Reset (R)\ pin. Trailing Edge triggering (A)\ and leading-edge-triggering (B) inputs are provided for triggering from either edge of the input pulse. On power up, the IC is reset. If either Mono is not used each input (on the unused device) must be terminated either high or low. The minimum value of external resistance, RX, is typically 500. The minimum value of external capacitance, CX, is 0pF. The calculation for the pulse width is tW= 0.7 RXCXat VCC= 4.5V. The ’HC221 and CD74HCT221 are dual monostable multivibrators with reset. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of RXand CXprovides a wide range of output pulse widths from the Q and Q\ terminals. Pulse triggering on the B input occurs at a particular voltage level and is not related to the rise and fall time of the trigger pulse. Once triggered, the outputs are independent of further trigger inputs on A\ and B. The output pulse can be terminated by a LOW level on the Reset (R)\ pin. Trailing Edge triggering (A)\ and leading-edge-triggering (B) inputs are provided for triggering from either edge of the input pulse. On power up, the IC is reset. If either Mono is not used each input (on the unused device) must be terminated either high or low. The minimum value of external resistance, RX, is typically 500. The minimum value of external capacitance, CX, is 0pF. The calculation for the pulse width is tW= 0.7 RXCXat VCC= 4.5V.

The CD74HC137, CD74HCT137, ’HC237, and CD74HCT237 are high speed silicon gate CMOS decoders well suited to memory address decoding or data routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic. Both circuits have three binary select inputs (A0, A1 and A2) that can be latched by an active High Latch Enable (LE) signal to isolate the outputs from select-input changes. A "Low" LE makes the output transparent to the input and the circuit functions as a one-of-eight decoder. Two Output Enable inputs (OE\1and OE0) are provided to simplify cascading and to facilitate demultiplexing. The demultiplexing function is accomplished by using the A0, A1, A2inputs to select the desired output and using one of the other Output Enable inputs as the data input while holding the other Output Enable input in its active state. In the CD74HC137 and CD74HCT137 the selected output is a "Low"; in the ’HC237 and CD74HCT237 the selected output is a "High". The CD74HC137, CD74HCT137, ’HC237, and CD74HCT237 are high speed silicon gate CMOS decoders well suited to memory address decoding or data routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic. Both circuits have three binary select inputs (A0, A1 and A2) that can be latched by an active High Latch Enable (LE) signal to isolate the outputs from select-input changes. A "Low" LE makes the output transparent to the input and the circuit functions as a one-of-eight decoder. Two Output Enable inputs (OE\1and OE0) are provided to simplify cascading and to facilitate demultiplexing. The demultiplexing function is accomplished by using the A0, A1, A2inputs to select the desired output and using one of the other Output Enable inputs as the data input while holding the other Output Enable input in its active state. In the CD74HC137 and CD74HCT137 the selected output is a "Low"; in the ’HC237 and CD74HCT237 the selected output is a "High".

High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer Inverting and Non-Inverting

High Speed CMOS Logic Quad-Bus Transceivers with 3-State Outputs

This device contains three independent 3-input NOR gates. Each gate performs the Boolean function Y =A + B + Cin positive logic. This device contains three independent 3-input NOR gates. Each gate performs the Boolean function Y =A + B + Cin positive logic.

The ’HC280 and ’HCT280 are 9-bit odd/even parity, generator checker devices. Both even and odd parity outputs are available for checking or generating parity for words up to nine bits long. Even parity is indicated (E output to any input of an additional HC/HCT280 parity checker. The ’HC280 and ’HCT280 are 9-bit odd/even parity, generator checker devices. Both even and odd parity outputs are available for checking or generating parity for words up to nine bits long. Even parity is indicated (E output to any input of an additional HC/HCT280 parity checker.

The ’HC259 and ’HCT299 are 8-bit shift/storage registers with three-state bus interface capability. The register has four synchronous-operating modes controlled by the two select inputs as shown in the mode select (S0, S1) table. The mode select, the serial data (DS0, DS7) and the parallel data (I/O0– I/O7) respond only to the low-to-high transition of the clock (CP) pulse. S0, S1 and data inputs must be one set-up time prior to the clock positive transition. The Master Reset (MR)\ is an asynchronous active low input. When MR\ output is low, the register is cleared regardless of the status of all other inputs. The register can be expanded by cascading same units by tying the serial output (Q0) to the serial data (DS7) input of the preceding register, and tying the serial output (Q7) to the serial data (DS0) input of the following register. Recirculating the (n x 8) bits is accomplished by tying the Q7 of the last stage to the DS0 of the first stage. The three-state input/output I(/O) port has three modes of operation: 1. Both output enable (OE1\ and OE2\) inputs are low and S0 or S1 or both are low, the data in the register is presented at the eight outputs. 2. When both S0 and S1 are high, I/O terminals are in the high impedance state but being input ports, ready for par-allel data to be loaded into eight registers with one clock transition regardless of the status of OE1\ and OE2\. 3. Either one of the two output enable inputs being high will force I/O terminals to be in the off-state. It is noted that each I/O terminal is a three-state output and a CMOS buffer input. The ’HC259 and ’HCT299 are 8-bit shift/storage registers with three-state bus interface capability. The register has four synchronous-operating modes controlled by the two select inputs as shown in the mode select (S0, S1) table. The mode select, the serial data (DS0, DS7) and the parallel data (I/O0– I/O7) respond only to the low-to-high transition of the clock (CP) pulse. S0, S1 and data inputs must be one set-up time prior to the clock positive transition. The Master Reset (MR)\ is an asynchronous active low input. When MR\ output is low, the register is cleared regardless of the status of all other inputs. The register can be expanded by cascading same units by tying the serial output (Q0) to the serial data (DS7) input of the preceding register, and tying the serial output (Q7) to the serial data (DS0) input of the following register. Recirculating the (n x 8) bits is accomplished by tying the Q7 of the last stage to the DS0 of the first stage. The three-state input/output I(/O) port has three modes of operation: 1. Both output enable (OE1\ and OE2\) inputs are low and S0 or S1 or both are low, the data in the register is presented at the eight outputs. 2. When both S0 and S1 are high, I/O terminals are in the high impedance state but being input ports, ready for par-allel data to be loaded into eight registers with one clock transition regardless of the status of OE1\ and OE2\. 3. Either one of the two output enable inputs being high will force I/O terminals to be in the off-state. It is noted that each I/O terminal is a three-state output and a CMOS buffer input.

This device contains one independent 8-input NAND gate. Each gate performs the Boolean function Y =A ● B ● C ● D ● E ● F ● G ● Hin positive logic. This device contains one independent 8-input NAND gate. Each gate performs the Boolean function Y =A ● B ● C ● D ● E ● F ● G ● Hin positive logic.

The CD54HC354, CD74HC354, and CD74HCT354 are data selectors/multiplexers that select one of eight sources. In both types, the data select bits S0, S1 and S2 are stored in transparent latches that are enabled by a low latch enable input, LE\. In the HC/HCT354 the data enable input, E\, controls transparent latches that pass data to the outputs when E\ is high and latches in new data when E\ is low. In both types the three-state outputs are controlled by three output-enable inputs OE1\, OE2\, and OE3. The CD54HC354, CD74HC354, and CD74HCT354 are data selectors/multiplexers that select one of eight sources. In both types, the data select bits S0, S1 and S2 are stored in transparent latches that are enabled by a low latch enable input, LE\. In the HC/HCT354 the data enable input, E\, controls transparent latches that pass data to the outputs when E\ is high and latches in new data when E\ is low. In both types the three-state outputs are controlled by three output-enable inputs OE1\, OE2\, and OE3.