Texas Instruments

CD4009UB and CD4010B Hex Buffer/Converters may be used as CMOS to TTL or DTL logic-level converters or CMOS high-sink-current drivers. The CD4049UB and CD4050B are preferred hex buffer replacements for the CD4009UB and CD4010B, respectively, in all applications except multiplexers. For applications not requiring high sink current or voltage conversion, the CD4069B Hex Inverter is recommended. The CD4009UB and CD4010B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). CD4009UB and CD4010B Hex Buffer/Converters may be used as CMOS to TTL or DTL logic-level converters or CMOS high-sink-current drivers. The CD4049UB and CD4050B are preferred hex buffer replacements for the CD4009UB and CD4010B, respectively, in all applications except multiplexers. For applications not requiring high sink current or voltage conversion, the CD4069B Hex Inverter is recommended. The CD4009UB and CD4010B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD40102B, and CD40103B consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102B is configured as two cascaded 4-bit BCD counters, and the CD40103B contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO-DEFECT output are active-low logic. In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE)\ input is high. The CARRY-OUT/ZERO-DEFECT (CO/ZD)\ output goes low when the count reaches zero if the CI/CE\ input is low, and remains low for one full clock period. When the SYNCHRONOUS PRESET-ENABLE (SPE)\ input is low, data at the JAM input is clocked input the counter on the next positive clock transition regardless of the state of the CI/CE\ input. When the ASYNCHRONOUS PRESET-ENABLE (APE)\ input is low, data at the JAM inputs is asynchronously forced into the counter regardless of the state of the SPE\, CI/CE\, or CLOCK inputs. JAM inputs JO-J7 represent two 4-bit BCD words for the CD40102B and a single 8-bit binary word for the CD40103B. When the CLEAR (CLR)\ input is low, the counter is asynchronously cleared to its maximum count (9910for the CD40102B and 25510for the CD40103B) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table. If all control inputs except CI/CE\ are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 or 256 clock pulses long. This causes the CO/ZD\ output to go low to enable the clock on each succeeding clock pulse. The CD40102B and CD40103B may be cascaded using the CI/CE\ input and CO/ZD\ output, in either a synchronous or ripple mode as shown in Figs. 21 and 22. The CD40102B and CD40103B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD40103B types also are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix). CD40102B, and CD40103B consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102B is configured as two cascaded 4-bit BCD counters, and the CD40103B contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO-DEFECT output are active-low logic. In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE)\ input is high. The CARRY-OUT/ZERO-DEFECT (CO/ZD)\ output goes low when the count reaches zero if the CI/CE\ input is low, and remains low for one full clock period. When the SYNCHRONOUS PRESET-ENABLE (SPE)\ input is low, data at the JAM input is clocked input the counter on the next positive clock transition regardless of the state of the CI/CE\ input. When the ASYNCHRONOUS PRESET-ENABLE (APE)\ input is low, data at the JAM inputs is asynchronously forced into the counter regardless of the state of the SPE\, CI/CE\, or CLOCK inputs. JAM inputs JO-J7 represent two 4-bit BCD words for the CD40102B and a single 8-bit binary word for the CD40103B. When the CLEAR (CLR)\ input is low, the counter is asynchronously cleared to its maximum count (9910for the CD40102B and 25510for the CD40103B) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table. If all control inputs except CI/CE\ are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 or 256 clock pulses long. This causes the CO/ZD\ output to go low to enable the clock on each succeeding clock pulse. The CD40102B and CD40103B may be cascaded using the CI/CE\ input and CO/ZD\ output, in either a synchronous or ripple mode as shown in Figs. 21 and 22. The CD40102B and CD40103B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD40103B types also are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix).

CD40102B, and CD40103B consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102B is configured as two cascaded 4-bit BCD counters, and the CD40103B contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO-DEFECT output are active-low logic. In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE)\ input is high. The CARRY-OUT/ZERO-DEFECT (CO/ZD)\ output goes low when the count reaches zero if the CI/CE\ input is low, and remains low for one full clock period. When the SYNCHRONOUS PRESET-ENABLE (SPE)\ input is low, data at the JAM input is clocked input the counter on the next positive clock transition regardless of the state of the CI/CE\ input. When the ASYNCHRONOUS PRESET-ENABLE (APE)\ input is low, data at the JAM inputs is asynchronously forced into the counter regardless of the state of the SPE\, CI/CE\, or CLOCK inputs. JAM inputs JO-J7 represent two 4-bit BCD words for the CD40102B and a single 8-bit binary word for the CD40103B. When the CLEAR (CLR)\ input is low, the counter is asynchronously cleared to its maximum count (9910for the CD40102B and 25510for the CD40103B) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table. If all control inputs except CI/CE\ are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 or 256 clock pulses long. This causes the CO/ZD\ output to go low to enable the clock on each succeeding clock pulse. The CD40102B and CD40103B may be cascaded using the CI/CE\ input and CO/ZD\ output, in either a synchronous or ripple mode as shown in Figs. 21 and 22. The CD40102B and CD40103B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD40103B types also are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix). CD40102B, and CD40103B consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102B is configured as two cascaded 4-bit BCD counters, and the CD40103B contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO-DEFECT output are active-low logic. In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE)\ input is high. The CARRY-OUT/ZERO-DEFECT (CO/ZD)\ output goes low when the count reaches zero if the CI/CE\ input is low, and remains low for one full clock period. When the SYNCHRONOUS PRESET-ENABLE (SPE)\ input is low, data at the JAM input is clocked input the counter on the next positive clock transition regardless of the state of the CI/CE\ input. When the ASYNCHRONOUS PRESET-ENABLE (APE)\ input is low, data at the JAM inputs is asynchronously forced into the counter regardless of the state of the SPE\, CI/CE\, or CLOCK inputs. JAM inputs JO-J7 represent two 4-bit BCD words for the CD40102B and a single 8-bit binary word for the CD40103B. When the CLEAR (CLR)\ input is low, the counter is asynchronously cleared to its maximum count (9910for the CD40102B and 25510for the CD40103B) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table. If all control inputs except CI/CE\ are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 or 256 clock pulses long. This causes the CO/ZD\ output to go low to enable the clock on each succeeding clock pulse. The CD40102B and CD40103B may be cascaded using the CI/CE\ input and CO/ZD\ output, in either a synchronous or ripple mode as shown in Figs. 21 and 22. The CD40102B and CD40103B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD40103B types also are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix).

CD40102B, and CD40103B consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102B is configured as two cascaded 4-bit BCD counters, and the CD40103B contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO-DEFECT output are active-low logic. In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE)\ input is high. The CARRY-OUT/ZERO-DEFECT (CO/ZD)\ output goes low when the count reaches zero if the CI/CE\ input is low, and remains low for one full clock period. When the SYNCHRONOUS PRESET-ENABLE (SPE)\ input is low, data at the JAM input is clocked input the counter on the next positive clock transition regardless of the state of the CI/CE\ input. When the ASYNCHRONOUS PRESET-ENABLE (APE)\ input is low, data at the JAM inputs is asynchronously forced into the counter regardless of the state of the SPE\, CI/CE\, or CLOCK inputs. JAM inputs JO-J7 represent two 4-bit BCD words for the CD40102B and a single 8-bit binary word for the CD40103B. When the CLEAR (CLR)\ input is low, the counter is asynchronously cleared to its maximum count (9910for the CD40102B and 25510for the CD40103B) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table. If all control inputs except CI/CE\ are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 or 256 clock pulses long. This causes the CO/ZD\ output to go low to enable the clock on each succeeding clock pulse. The CD40102B and CD40103B may be cascaded using the CI/CE\ input and CO/ZD\ output, in either a synchronous or ripple mode as shown in Figs. 21 and 22. The CD40102B and CD40103B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD40103B types also are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix). CD40102B, and CD40103B consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102B is configured as two cascaded 4-bit BCD counters, and the CD40103B contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO-DEFECT output are active-low logic. In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE)\ input is high. The CARRY-OUT/ZERO-DEFECT (CO/ZD)\ output goes low when the count reaches zero if the CI/CE\ input is low, and remains low for one full clock period. When the SYNCHRONOUS PRESET-ENABLE (SPE)\ input is low, data at the JAM input is clocked input the counter on the next positive clock transition regardless of the state of the CI/CE\ input. When the ASYNCHRONOUS PRESET-ENABLE (APE)\ input is low, data at the JAM inputs is asynchronously forced into the counter regardless of the state of the SPE\, CI/CE\, or CLOCK inputs. JAM inputs JO-J7 represent two 4-bit BCD words for the CD40102B and a single 8-bit binary word for the CD40103B. When the CLEAR (CLR)\ input is low, the counter is asynchronously cleared to its maximum count (9910for the CD40102B and 25510for the CD40103B) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table. If all control inputs except CI/CE\ are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 or 256 clock pulses long. This causes the CO/ZD\ output to go low to enable the clock on each succeeding clock pulse. The CD40102B and CD40103B may be cascaded using the CI/CE\ input and CO/ZD\ output, in either a synchronous or ripple mode as shown in Figs. 21 and 22. The CD40102B and CD40103B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD40103B types also are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix).

CD40105B is a low-power first-in-first-out (FIFO) "elastic" storage register that can store 16 4-bit words. It is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A "1" signifies that the position's data is filed and a "0" denotes a vacancy in that positiion. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the "0" state and sees a "1" in the preceding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to "0". The first and last control flip-flops have buffered outputs. Since all empty locations "bubble" automatically to the input end, and all valid data ripple through to the output end, the status of the first control flip-flop (DATA-IN READY) indicates if the FIFO is full, and the status of the last flip-flop (DATA-OUT READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output. Loading Data - Data can be entered whenever the DATA-IN READY (DIR) flag is high, by a low to high transition on the SHIFT-IN (SI) input. This input must go low momentarily before the next word is accepted by the FIFO. The DIR flag will go low momentarily, until the data have been transferred to the second location. The flag will remian low when all 16-word locations are filled with valid data, and further pulses on the SI input will be ignored until DIR goes high. Unloading Data - As soon as the first work has rippled to the output, DATA-OUT READY (DOR) goes high, and data can be removed by a falling edge on the SO input. This falling edge causes the DOR signal to go low while the word on the output is dumped and the next word moves to the output. As long as valid data are available in the FIFO, the DOR signal will go high again signifying that the next word is ready at the output. When the FIFO is empty, DOR will remain low, and any further commands will be ignored until a "1" marker ripples down to the last control register, when DOR goes high. Unloading of data is inhibited while the 3-state control input is high. The 3-state control signal should not be shifted from high to low (data outputs turned on) while the SHIFT-OUT is a logic 0. This level change would cause the first word to be shifted out (unloaded) immediately and the data to be lost. Cascading - The CD40105B can be cascaded to form longer registers simply by connecting the DIR to SO and DOR to SI. In the cascaded mode, a MASTER RESET pulse must be applied after the supply voltage is turned on. For words wider than 4 bits, the DIR and the DOR outputs must be gated together with AND gates. Their outputs drive the SI and SO inputs in paralled, if expanding is done in both directions (see Figs. 3 and 15). 3-State Outputs - In order to facilitate data busing, 3-state outputs are provided on the data output lines, while the load condition of the register can be detected by the state of the DOR output. Master Reset - A high on the MASTER RESET (MR) sets all the contol logic marker bits to "0". DOR goes low and DIR goes high. The contents of the data register are not changed, only declared invalid, and will be superseded when the first word is loaded. The shift-in must be low during Master Reset. The CD40105B types are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes), 16-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix). CD40105B is a low-power first-in-first-out (FIFO) "elastic" storage register that can store 16 4-bit words. It is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A "1" signifies that the position's data is filed and a "0" denotes a vacancy in that positiion. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the "0" state and sees a "1" in the preceding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to "0". The first and last control flip-flops have buffered outputs. Since all empty locations "bubble" automatically to the input end, and all valid data ripple through to the output end, the status of the first control flip-flop (DATA-IN READY) indicates if the FIFO is full, and the status of the last flip-flop (DATA-OUT READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output. Loading Data - Data can be entered whenever the DATA-IN READY (DIR) flag is high, by a low to high transition on the SHIFT-IN (SI) input. This input must go low momentarily before the next word is accepted by the FIFO. The DIR flag will go low momentarily, until the data have been transferred to the second location. The flag will remian low when all 16-word locations are filled with valid data, and further pulses on the SI input will be ignored until DIR goes high. Unloading Data - As soon as the first work has rippled to the output, DATA-OUT READY (DOR) goes high, and data can be removed by a falling edge on the SO input. This falling edge causes the DOR signal to go low while the word on the output is dumped and the next word moves to the output. As long as valid data are available in the FIFO, the DOR signal will go high again signifying that the next word is ready at the output. When the FIFO is empty, DOR will remain low, and any further commands will be ignored until a "1" marker ripples down to the last control register, when DOR goes high. Unloading of data is inhibited while the 3-state control input is high. The 3-state control signal should not be shifted from high to low (data outputs turned on) while the SHIFT-OUT is a logic 0. This level change would cause the first word to be shifted out (unloaded) immediately and the data to be lost. Cascading - The CD40105B can be cascaded to form longer registers simply by connecting the DIR to SO and DOR to SI. In the cascaded mode, a MASTER RESET pulse must be applied after the supply voltage is turned on. For words wider than 4 bits, the DIR and the DOR outputs must be gated together with AND gates. Their outputs drive the SI and SO inputs in paralled, if expanding is done in both directions (see Figs. 3 and 15). 3-State Outputs - In order to facilitate data busing, 3-state outputs are provided on the data output lines, while the load condition of the register can be detected by the state of the DOR output. Master Reset - A high on the MASTER RESET (MR) sets all the contol logic marker bits to "0". DOR goes low and DIR goes high. The contents of the data register are not changed, only declared invalid, and will be superseded when the first word is loaded. The shift-in must be low during Master Reset. The CD40105B types are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes), 16-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).

CD40105B is a low-power first-in-first-out (FIFO) "elastic" storage register that can store 16 4-bit words. It is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A "1" signifies that the position's data is filed and a "0" denotes a vacancy in that positiion. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the "0" state and sees a "1" in the preceding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to "0". The first and last control flip-flops have buffered outputs. Since all empty locations "bubble" automatically to the input end, and all valid data ripple through to the output end, the status of the first control flip-flop (DATA-IN READY) indicates if the FIFO is full, and the status of the last flip-flop (DATA-OUT READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output. Loading Data - Data can be entered whenever the DATA-IN READY (DIR) flag is high, by a low to high transition on the SHIFT-IN (SI) input. This input must go low momentarily before the next word is accepted by the FIFO. The DIR flag will go low momentarily, until the data have been transferred to the second location. The flag will remian low when all 16-word locations are filled with valid data, and further pulses on the SI input will be ignored until DIR goes high. Unloading Data - As soon as the first work has rippled to the output, DATA-OUT READY (DOR) goes high, and data can be removed by a falling edge on the SO input. This falling edge causes the DOR signal to go low while the word on the output is dumped and the next word moves to the output. As long as valid data are available in the FIFO, the DOR signal will go high again signifying that the next word is ready at the output. When the FIFO is empty, DOR will remain low, and any further commands will be ignored until a "1" marker ripples down to the last control register, when DOR goes high. Unloading of data is inhibited while the 3-state control input is high. The 3-state control signal should not be shifted from high to low (data outputs turned on) while the SHIFT-OUT is a logic 0. This level change would cause the first word to be shifted out (unloaded) immediately and the data to be lost. Cascading - The CD40105B can be cascaded to form longer registers simply by connecting the DIR to SO and DOR to SI. In the cascaded mode, a MASTER RESET pulse must be applied after the supply voltage is turned on. For words wider than 4 bits, the DIR and the DOR outputs must be gated together with AND gates. Their outputs drive the SI and SO inputs in paralled, if expanding is done in both directions (see Figs. 3 and 15). 3-State Outputs - In order to facilitate data busing, 3-state outputs are provided on the data output lines, while the load condition of the register can be detected by the state of the DOR output. Master Reset - A high on the MASTER RESET (MR) sets all the contol logic marker bits to "0". DOR goes low and DIR goes high. The contents of the data register are not changed, only declared invalid, and will be superseded when the first word is loaded. The shift-in must be low during Master Reset. The CD40105B types are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes), 16-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix). CD40105B is a low-power first-in-first-out (FIFO) "elastic" storage register that can store 16 4-bit words. It is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A "1" signifies that the position's data is filed and a "0" denotes a vacancy in that positiion. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the "0" state and sees a "1" in the preceding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to "0". The first and last control flip-flops have buffered outputs. Since all empty locations "bubble" automatically to the input end, and all valid data ripple through to the output end, the status of the first control flip-flop (DATA-IN READY) indicates if the FIFO is full, and the status of the last flip-flop (DATA-OUT READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output. Loading Data - Data can be entered whenever the DATA-IN READY (DIR) flag is high, by a low to high transition on the SHIFT-IN (SI) input. This input must go low momentarily before the next word is accepted by the FIFO. The DIR flag will go low momentarily, until the data have been transferred to the second location. The flag will remian low when all 16-word locations are filled with valid data, and further pulses on the SI input will be ignored until DIR goes high. Unloading Data - As soon as the first work has rippled to the output, DATA-OUT READY (DOR) goes high, and data can be removed by a falling edge on the SO input. This falling edge causes the DOR signal to go low while the word on the output is dumped and the next word moves to the output. As long as valid data are available in the FIFO, the DOR signal will go high again signifying that the next word is ready at the output. When the FIFO is empty, DOR will remain low, and any further commands will be ignored until a "1" marker ripples down to the last control register, when DOR goes high. Unloading of data is inhibited while the 3-state control input is high. The 3-state control signal should not be shifted from high to low (data outputs turned on) while the SHIFT-OUT is a logic 0. This level change would cause the first word to be shifted out (unloaded) immediately and the data to be lost. Cascading - The CD40105B can be cascaded to form longer registers simply by connecting the DIR to SO and DOR to SI. In the cascaded mode, a MASTER RESET pulse must be applied after the supply voltage is turned on. For words wider than 4 bits, the DIR and the DOR outputs must be gated together with AND gates. Their outputs drive the SI and SO inputs in paralled, if expanding is done in both directions (see Figs. 3 and 15). 3-State Outputs - In order to facilitate data busing, 3-state outputs are provided on the data output lines, while the load condition of the register can be detected by the state of the DOR output. Master Reset - A high on the MASTER RESET (MR) sets all the contol logic marker bits to "0". DOR goes low and DIR goes high. The contents of the data register are not changed, only declared invalid, and will be superseded when the first word is loaded. The shift-in must be low during Master Reset. The CD40105B types are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes), 16-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).

The CD40106B device consists of six Schmitt-Trigger inputs. Each circuit functions as an inverter with Schmitt-Trigger input. The trigger switches at different points for positive- and negative-going signals. The difference between the positive-going voltage (VP) and the negative-going voltages (VN) is defined as hysteresis voltage (VH). The CD40106B device is supplied in ceramic packaging (J) as well as standard packaging (D, N, NS, PW). All CD40106B devices are rated for –55°C to +125°C ambient temperature operation. The CD40106B device consists of six Schmitt-Trigger inputs. Each circuit functions as an inverter with Schmitt-Trigger input. The trigger switches at different points for positive- and negative-going signals. The difference between the positive-going voltage (VP) and the negative-going voltages (VN) is defined as hysteresis voltage (VH). The CD40106B device is supplied in ceramic packaging (J) as well as standard packaging (D, N, NS, PW). All CD40106B devices are rated for –55°C to +125°C ambient temperature operation.

The CD40107B is a dual 2-input NAND buffer/driver containing two independent 2-input NAND buffers with open-drain single n-channel transistor outputs. This device features a wired-OR capability and high output sink current capability (136 mA typ. at VDD= 10 V, VDS= 1 V). The CD40107B is supplied in 8-lead hermetic dual-in-line ceramic packages (F3A suffix), 8-lead dual-in-line plastic packages (E suffix), 8-lead small-outline packages (M, M96, MT, and PSR suffixes), and 8-lead thin shrink small-outline packages (PW and PWR suffixes). The CD40107B is a dual 2-input NAND buffer/driver containing two independent 2-input NAND buffers with open-drain single n-channel transistor outputs. This device features a wired-OR capability and high output sink current capability (136 mA typ. at VDD= 10 V, VDS= 1 V). The CD40107B is supplied in 8-lead hermetic dual-in-line ceramic packages (F3A suffix), 8-lead dual-in-line plastic packages (E suffix), 8-lead small-outline packages (M, M96, MT, and PSR suffixes), and 8-lead thin shrink small-outline packages (PW and PWR suffixes).

CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = VCCand logical 0 = VSSto a higher-voltage output signal (E, F, G, H) with logical 1 = VDDand logical 0 = VSS. The CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSSand at least 0.7 VCC; VCCmay exceed VDD, and input signals may exceed VCCand VDD. When operated in the mode VCC> VDD, the CD40109 will operate as a high-to-low level-shifter. The CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output. The CD40109B-Series types are supplied in 16-lead ceramic dual-in-line packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = VCCand logical 0 = VSSto a higher-voltage output signal (E, F, G, H) with logical 1 = VDDand logical 0 = VSS. The CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSSand at least 0.7 VCC; VCCmay exceed VDD, and input signals may exceed VCCand VDD. When operated in the mode VCC> VDD, the CD40109 will operate as a high-to-low level-shifter. The CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output. The CD40109B-Series types are supplied in 16-lead ceramic dual-in-line packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = VCCand logical 0 = VSSto a higher-voltage output signal (E, F, G, H) with logical 1 = VDDand logical 0 = VSS. The CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSSand at least 0.7 VCC; VCCmay exceed VDD, and input signals may exceed VCCand VDD. When operated in the mode VCC> VDD, the CD40109 will operate as a high-to-low level-shifter. The CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output. The CD40109B-Series types are supplied in 16-lead ceramic dual-in-line packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = VCCand logical 0 = VSSto a higher-voltage output signal (E, F, G, H) with logical 1 = VDDand logical 0 = VSS. The CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSSand at least 0.7 VCC; VCCmay exceed VDD, and input signals may exceed VCCand VDD. When operated in the mode VCC> VDD, the CD40109 will operate as a high-to-low level-shifter. The CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output. The CD40109B-Series types are supplied in 16-lead ceramic dual-in-line packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).