CD40109B-MIL Series

CMOS Quad Low-to-High Voltage Level Shifter (20V Rating)

Catalog

CMOS Quad Low-to-High Voltage Level Shifter (20V Rating)

Part	Translator Type	Voltage - VCCB [Min]	Voltage - VCCB [Max]	Output Type	Number of Circuits	Supplier Device Package	Channel Type	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Package / Case	Mounting Type
Texas Instruments CD40109BF3A	Voltage Level	3 V	18 V	Tri-State	4	16-CDIP	Unidirectional	125 °C	-55 °C	0.3 in 7.62 mm	16-CDIP	Through Hole

Catalog

CMOS Quad Low-to-High Voltage Level Shifter (20V Rating)

Key Features

• Independence of power supply sequence considerations - VCCcan exceed VDD, input signals can exceed both VCCand VDDUp and down level-shifting capabilityThree-state outputs with separate enable controlsStandardized, symmetrical output characteristics100% tested for quiescent current at 20 VMaximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CNoise margin (full package-temperature range):= 1 V at VCC= 5 V, VDD= 10 V= 2 V at VCC= 10 V, VDD= 15 V5-V, 10-V, and 15-V parametric ratingsMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"Applications:High-or-low level-shifting with three-state outputs for unidirectional or bidirectional bussing.Isolation of logic subsystems using separate power supplies from supply sequencing, supply loss and supply regulation considerationsData sheet acquired from Harris SemiconductorIndependence of power supply sequence considerations - VCCcan exceed VDD, input signals can exceed both VCCand VDDUp and down level-shifting capabilityThree-state outputs with separate enable controlsStandardized, symmetrical output characteristics100% tested for quiescent current at 20 VMaximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CNoise margin (full package-temperature range):= 1 V at VCC= 5 V, VDD= 10 V= 2 V at VCC= 10 V, VDD= 15 V5-V, 10-V, and 15-V parametric ratingsMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"Applications:High-or-low level-shifting with three-state outputs for unidirectional or bidirectional bussing.Isolation of logic subsystems using separate power supplies from supply sequencing, supply loss and supply regulation considerationsData sheet acquired from Harris Semiconductor

Description

CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = VCCand logical 0 = VSSto a higher-voltage output signal (E, F, G, H) with logical 1 = VDDand logical 0 = VSS. The CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSSand at least 0.7 VCC; VCCmay exceed VDD, and input signals may exceed VCCand VDD. When operated in the mode VCC> VDD, the CD40109 will operate as a high-to-low level-shifter. The CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output. The CD40109B-Series types are supplied in 16-lead ceramic dual-in-line packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = VCCand logical 0 = VSSto a higher-voltage output signal (E, F, G, H) with logical 1 = VDDand logical 0 = VSS. The CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSSand at least 0.7 VCC; VCCmay exceed VDD, and input signals may exceed VCCand VDD. When operated in the mode VCC> VDD, the CD40109 will operate as a high-to-low level-shifter. The CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output. The CD40109B-Series types are supplied in 16-lead ceramic dual-in-line packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).