The ´BCT623 bus transceiver is designed for asynchronous communication between data buses. The control function implementation allows for maximum flexibility in timing. The ´BCT623 provides true data at its outputs. This device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic levels at the output-enable (OEAB and) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated. The dual-enable configuration gives the transceivers the capability of storing data by simultaneously enabling OEAB and. Each output reinforces its input in this configuration. When both OEAB andare enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (16 in all) will remain at their last states. The SN54BCT623 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT623 is characterized for operation from 0°C to 70°C. The ´BCT623 bus transceiver is designed for asynchronous communication between data buses. The control function implementation allows for maximum flexibility in timing. The ´BCT623 provides true data at its outputs. This device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic levels at the output-enable (OEAB and) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated. The dual-enable configuration gives the transceivers the capability of storing data by simultaneously enabling OEAB and. Each output reinforces its input in this configuration. When both OEAB andare enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (16 in all) will remain at their last states. The SN54BCT623 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT623 is characterized for operation from 0°C to 70°C.

These voltage-controlled oscillators (VCOs) are improved versions of the original VCO family: SN54LS124, SN54LS324 thru SN54LS327, SN74LS124, and SN74LS324 thru SN74LS327. These new devices feature improved voltage-to-frequency linearity, range, and compensation. With the exception of the 'LS624 and 'LS628, all of these devices feature two independent VCOs in a single monolithic chip. The 'LS624, 'LS625, 'LS626, and 'LS628 have complementary Z outputs. The output frequency for each VCO is established by a single external component (either a capacitor or crystal) in combination with voltage-sensitive inputs used for frequency control and frequency range. Each device has a voltage-sensitive input for frequency control; however, the 'LS624, 'LS628, and 'LS629 devices also have one for frequency range. (See Figures 1 thru 6). The 'LS628 offers more precise temperature compensation than its 'LS624 counterpart. The 'LS624 features a 600 ohm internal timing resistor. The 'LS628 requires a timing resistor to be connected externally across Rextpins. Temperature compensation will be improved due to the temperature coefficient of the external resistor. Figure 3 and Figure 6 contain the necessary information to choose the proper capacitor value to obtain the desired operating frequency. A single 5-volt supply can be used: however, one set of supply voltage and ground pins (VCCand GND) is provided for the enable, synchronization-gating, and output sections, and a separate set (OSC VCCand OSC GND) is provided for the oscillator and associated frequency-control circuits so that effective isolation can be accomplished in the system. For operation of frequencies greater than 10 MHz, it is recommended that two independent supplies be used. Disabling either VCO of the 'LS625 and 'LS625 and 'LS627 can be achieved by removing the appropriate OSC VCC. An enable input is provided on the 'LS624, 'LS626, 'LS628, and 'LS629. When the enable input is low, the output is enabled: when the enable input is high, the internal oscillator is disabled, Y is high, and Z is low. Caution! Crosstalk may occur in the dual devices ('LS625, 'LS626, 'LS627 and 'LS629) when both VCOs are operated simultaneously. To minimize crosstalk, either of the following are recommended: (A) If frequencies are widely separated, use a 10-μh inductor between VCCpins. (B) If frequencies are closely spaced, use two separate VCCsupplies or place two series diodes between the VCCpins. The pulse-synchronization-gating section ensures that the first output pulse is neither clipped nor extended. The duty cycle of the square-wave output is fixed at approximately 50 percent. The SN54LS624 thru SN54LS629 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS624 thru SN74LS629 are characterized for operation from 0°C to 70°C. These voltage-controlled oscillators (VCOs) are improved versions of the original VCO family: SN54LS124, SN54LS324 thru SN54LS327, SN74LS124, and SN74LS324 thru SN74LS327. These new devices feature improved voltage-to-frequency linearity, range, and compensation. With the exception of the 'LS624 and 'LS628, all of these devices feature two independent VCOs in a single monolithic chip. The 'LS624, 'LS625, 'LS626, and 'LS628 have complementary Z outputs. The output frequency for each VCO is established by a single external component (either a capacitor or crystal) in combination with voltage-sensitive inputs used for frequency control and frequency range. Each device has a voltage-sensitive input for frequency control; however, the 'LS624, 'LS628, and 'LS629 devices also have one for frequency range. (See Figures 1 thru 6). The 'LS628 offers more precise temperature compensation than its 'LS624 counterpart. The 'LS624 features a 600 ohm internal timing resistor. The 'LS628 requires a timing resistor to be connected externally across Rextpins. Temperature compensation will be improved due to the temperature coefficient of the external resistor. Figure 3 and Figure 6 contain the necessary information to choose the proper capacitor value to obtain the desired operating frequency. A single 5-volt supply can be used: however, one set of supply voltage and ground pins (VCCand GND) is provided for the enable, synchronization-gating, and output sections, and a separate set (OSC VCCand OSC GND) is provided for the oscillator and associated frequency-control circuits so that effective isolation can be accomplished in the system. For operation of frequencies greater than 10 MHz, it is recommended that two independent supplies be used. Disabling either VCO of the 'LS625 and 'LS625 and 'LS627 can be achieved by removing the appropriate OSC VCC. An enable input is provided on the 'LS624, 'LS626, 'LS628, and 'LS629. When the enable input is low, the output is enabled: when the enable input is high, the internal oscillator is disabled, Y is high, and Z is low. Caution! Crosstalk may occur in the dual devices ('LS625, 'LS626, 'LS627 and 'LS629) when both VCOs are operated simultaneously. To minimize crosstalk, either of the following are recommended: (A) If frequencies are widely separated, use a 10-μh inductor between VCCpins. (B) If frequencies are closely spaced, use two separate VCCsupplies or place two series diodes between the VCCpins. The pulse-synchronization-gating section ensures that the first output pulse is neither clipped nor extended. The duty cycle of the square-wave output is fixed at approximately 50 percent. The SN54LS624 thru SN54LS629 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS624 thru SN74LS629 are characterized for operation from 0°C to 70°C.

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the SN54ABT240, SN74ABT240A, SN54ABT241, and SN74ABT241A, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE)\ inputs, and complementary OE and OE\ inputs. The SN54ABT244 and SN74ABT244A are organized as two 4-bit buffers/line drivers with separate OE\ inputs. When OE\ is low, the devices pass noninverted data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT244 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT244A is characterized for operation from -40°C to 85°C. These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the SN54ABT240, SN74ABT240A, SN54ABT241, and SN74ABT241A, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE)\ inputs, and complementary OE and OE\ inputs. The SN54ABT244 and SN74ABT244A are organized as two 4-bit buffers/line drivers with separate OE\ inputs. When OE\ is low, the devices pass noninverted data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT244 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT244A is characterized for operation from -40°C to 85°C.

These octal bus transceivers are designed for asynchronous communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so the buses are effectively isolated. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. These octal bus transceivers are designed for asynchronous communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so the buses are effectively isolated. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The ’ACT10 devices contain three independent 3-input NAND gates. The devices perform the Boolean functions Y = A • B • C or Y = A + B + C in positive logic. The ’ACT10 devices contain three independent 3-input NAND gates. The devices perform the Boolean functions Y = A • B • C or Y = A + B + C in positive logic.

The \x92FCT240T devices are octal buffers and line drivers designed to be employed as memory address drivers, clock drivers, and bus-oriented transmitters/receivers. These devices provide speed and drive capabilities equivalent to their fastest bipolar logic counterparts, while reducing power consumption. The input and output voltage levels allow direct interface with TTL, NMOS, and CMOS devices without external components. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The \x92FCT240T devices are octal buffers and line drivers designed to be employed as memory address drivers, clock drivers, and bus-oriented transmitters/receivers. These devices provide speed and drive capabilities equivalent to their fastest bipolar logic counterparts, while reducing power consumption. The input and output voltage levels allow direct interface with TTL, NMOS, and CMOS devices without external components. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The \x92FCT245T devices contain eight noninverting bidirectional buffers with 3-state outputs and are intended for bus-oriented applications. The transmit/receive (T/R\) input determines the direction of data flow through these bidirectional transceivers. Transmit (active high) enables data from A ports to B ports. The output enable (OE\), when high, disables both the A and B ports by putting them in the high-impedance state. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The \x92FCT245T devices contain eight noninverting bidirectional buffers with 3-state outputs and are intended for bus-oriented applications. The transmit/receive (T/R\) input determines the direction of data flow through these bidirectional transceivers. Transmit (active high) enables data from A ports to B ports. The output enable (OE\), when high, disables both the A and B ports by putting them in the high-impedance state. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The \x92FCT273T devices consist of eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered-clock (CP) and master-reset (MR\) inputs load and reset all flip-flops simultaneously. These devices are edge-triggered registers. The state of each D input (one setup time before the low-to-high clock transition) is transferred to the corresponding flip-flop\x92s Q output. All outputs are forced low by a low logic level on the MR\ input. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The \x92FCT273T devices consist of eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered-clock (CP) and master-reset (MR\) inputs load and reset all flip-flops simultaneously. These devices are edge-triggered registers. The state of each D input (one setup time before the low-to-high clock transition) is transferred to the corresponding flip-flop\x92s Q output. All outputs are forced low by a low logic level on the MR\ input. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.