| Development Boards, Kits, Programmers | 1 | Obsolete | |
UCC358016V active clamp current mode PWM controller with N-channel clamp FET and 16V turn-on, 0°C to 70°C | DC DC Switching Controllers | 17 | Active | The UCC3580 family of PWM controllers is designed to implement a variety of active clamp/reset and synchronous rectifier switching converter topologies. While containing all the necessary functions for fixed frequency, high performance pulse width modulation, the additional feature of this design is the inclusion of an auxiliary switch driver which complements the main power switch, and with a programmable deadtime or delay between each transition. The active clamp/reset technique allows operation of single ended converters beyond 50% duty cycle while reducing voltage stresses on the switches, and allows a greater flux swing for the power transformer. This approach also allows a reduction in switching losses by recovering energy stored in parasitic elements such as leakage inductance and switch capacitance.
The oscillator is programmed with two resistors and a capacitor to set switching frequency and maximum duty cycle. A separate synchronized ramp provides a voltage feedforward pulse width modulation and a programmed maximum volt-second limit. The generated clock from the oscillator contains both frequency and maximum duty cycle information.
The main gate drive output (OUT1) is controlled by the pulse width modulator. The second output (OUT2) is intended to activate an auxiliary switch during the off time of the main switch, except that between each transition there is deadtime where both switches are off, programmed by a single external resistor. This design offers two options for OUT2, normal and inverted. In the -1 and -2 versions, OUT2 is normal and can be used to drive PMOS FETs. In the -3 and -4 versions, OUT2 is inverted and can be used to drive NMOS FETs. In all versions, both the main and auxiliary switches are held off prior to startup and when the PWM command goes to zero duty cycle. During fault conditions, OUT1 is held off while OUT2 operates at maximum duty cycle with a guaranteed off time equal to the sum of the two deadtimes.
Undervoltage lockout monitors supply voltage (VDD), the precision reference (REF), input line voltage (LINE), and the shutdown comparator (SHTDWN). If after any of these four have sensed a fault condition, recovery to full operation is initiated with a soft start. VDD thresholds, on and off, are 15V and 8.5V for the -2 and -4 versions, 9V and 8.5V for the -1 and -3 versions.
The UCC1580-x is specified for operation over the military temperature range of –55°C to 125°C. The UCC2580-x is specified from –40°C to 85°C. The UCC3580-x is specified from 0°C to 70°C. Package options include 16-pin surface mount and dual in-line.
The UCC3580 family of PWM controllers is designed to implement a variety of active clamp/reset and synchronous rectifier switching converter topologies. While containing all the necessary functions for fixed frequency, high performance pulse width modulation, the additional feature of this design is the inclusion of an auxiliary switch driver which complements the main power switch, and with a programmable deadtime or delay between each transition. The active clamp/reset technique allows operation of single ended converters beyond 50% duty cycle while reducing voltage stresses on the switches, and allows a greater flux swing for the power transformer. This approach also allows a reduction in switching losses by recovering energy stored in parasitic elements such as leakage inductance and switch capacitance.
The oscillator is programmed with two resistors and a capacitor to set switching frequency and maximum duty cycle. A separate synchronized ramp provides a voltage feedforward pulse width modulation and a programmed maximum volt-second limit. The generated clock from the oscillator contains both frequency and maximum duty cycle information.
The main gate drive output (OUT1) is controlled by the pulse width modulator. The second output (OUT2) is intended to activate an auxiliary switch during the off time of the main switch, except that between each transition there is deadtime where both switches are off, programmed by a single external resistor. This design offers two options for OUT2, normal and inverted. In the -1 and -2 versions, OUT2 is normal and can be used to drive PMOS FETs. In the -3 and -4 versions, OUT2 is inverted and can be used to drive NMOS FETs. In all versions, both the main and auxiliary switches are held off prior to startup and when the PWM command goes to zero duty cycle. During fault conditions, OUT1 is held off while OUT2 operates at maximum duty cycle with a guaranteed off time equal to the sum of the two deadtimes.
Undervoltage lockout monitors supply voltage (VDD), the precision reference (REF), input line voltage (LINE), and the shutdown comparator (SHTDWN). If after any of these four have sensed a fault condition, recovery to full operation is initiated with a soft start. VDD thresholds, on and off, are 15V and 8.5V for the -2 and -4 versions, 9V and 8.5V for the -1 and -3 versions.
The UCC1580-x is specified for operation over the military temperature range of –55°C to 125°C. The UCC2580-x is specified from –40°C to 85°C. The UCC3580-x is specified from 0°C to 70°C. Package options include 16-pin surface mount and dual in-line. |
| DC DC Switching Controllers | 3 | Active | |
UCC3583Switch mode Secondary side Post Regulator with 0°C to 70°C | Integrated Circuits (ICs) | 6 | Active | The UCC3583 is a synchronizable secondary side post regulator for precision regulation of the auxiliary outputs of multiple output power supplies. It contains a leading edge pulse width modulator, which generates the gate drive signal for a FET power switch connected in series with the rectifying diode. The turn-on of the power switch is delayed from the leading edge of the secondary power pulse to regulate the output voltage. The UCC3583 contains a ramp generator slaved to the secondary power pulse, a voltage error amplifier, a current error amplifier, a PWM comparator and associated logic, a gate driver, a precision reference, and protection circuitry.
The ramp discharge and termination of the gate drive signal are triggered by the synchronization pulse, typically derived from the falling edge of the transformer secondary voltage. The ramp starts charging again once its low threshold is reached. The gate drive signal is turned on when the ramp voltage exceeds the control voltage. This leading edge modulation technique prevents instability when the UCC3583 is used in peak current mode primary controlled systems.
The controller operates from a floating power supply referenced to the output voltage being controlled. It features an undervoltage lockout (UVLO) circuit, a soft start circuit, and an averaging current limit amplifier. The current limit can be programmed to be proportional to the output voltage, thus achieving foldback operation to minimize the dissipation under short circuit conditions.
The UCC3583 is a synchronizable secondary side post regulator for precision regulation of the auxiliary outputs of multiple output power supplies. It contains a leading edge pulse width modulator, which generates the gate drive signal for a FET power switch connected in series with the rectifying diode. The turn-on of the power switch is delayed from the leading edge of the secondary power pulse to regulate the output voltage. The UCC3583 contains a ramp generator slaved to the secondary power pulse, a voltage error amplifier, a current error amplifier, a PWM comparator and associated logic, a gate driver, a precision reference, and protection circuitry.
The ramp discharge and termination of the gate drive signal are triggered by the synchronization pulse, typically derived from the falling edge of the transformer secondary voltage. The ramp starts charging again once its low threshold is reached. The gate drive signal is turned on when the ramp voltage exceeds the control voltage. This leading edge modulation technique prevents instability when the UCC3583 is used in peak current mode primary controlled systems.
The controller operates from a floating power supply referenced to the output voltage being controlled. It features an undervoltage lockout (UVLO) circuit, a soft start circuit, and an averaging current limit amplifier. The current limit can be programmed to be proportional to the output voltage, thus achieving foldback operation to minimize the dissipation under short circuit conditions. |
| Integrated Circuits (ICs) | 6 | Active | |
| Special Purpose Regulators | 2 | Obsolete | |
| Integrated Circuits (ICs) | 6 | Active | |
| Power Management (PMIC) | 7 | Active | |
UCC373229-A/9-A single-channel gate driver with split outputs, 25-ns prop delay, and enable | Integrated Circuits (ICs) | 9 | Active | The UCC2732x/UCC3732x family of high-speed drivers deliver 9 A of peak drive current in an industry standard pinout. These drivers can drive the largest of MOSFETs for systems requiring extreme Miller current due to high dV/dt transitions. This eliminates additional external circuits and can replace multiple components to reduce space, design complexity, and assembly cost. Two standard logic options are offered, inverting (UCC37321) and noninverting (UCC37322).
The UCC2732x/UCC3732x family of high-speed drivers deliver 9 A of peak drive current in an industry standard pinout. These drivers can drive the largest of MOSFETs for systems requiring extreme Miller current due to high dV/dt transitions. This eliminates additional external circuits and can replace multiple components to reduce space, design complexity, and assembly cost. Two standard logic options are offered, inverting (UCC37321) and noninverting (UCC37322). |
UCC373234-A/4-A dual-channel gate driver with inverting inputs | Integrated Circuits (ICs) | 5 | Active | The UCC2732x and UCC3732x family of high-speed dual-MOSFET Drivers deliver 4-A source and 4-A sink peak current to effectively drive MOSFETs where it is needed most at the Miller Plateau Region. A unique BiPolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply voltages. Three standard logic options are offered — dual-inverting, dual-noninverting, and one-inverting and one-noninverting driver. Input thresholds are based on TTL and CMOS and independent of supply voltage and feature wide input hysteresis offering excellent noise immunity. The UCC2732x and UCC3732x family is available in the standard SOIC-8 (D) as well as the thermally enhanced -8pin PowerPAD MSOP package (DGN), drastically lowering thermal resistance to improve long term reliability.
The UCC2732x and UCC3732x family of high-speed dual-MOSFET Drivers deliver 4-A source and 4-A sink peak current to effectively drive MOSFETs where it is needed most at the Miller Plateau Region. A unique BiPolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply voltages. Three standard logic options are offered — dual-inverting, dual-noninverting, and one-inverting and one-noninverting driver. Input thresholds are based on TTL and CMOS and independent of supply voltage and feature wide input hysteresis offering excellent noise immunity. The UCC2732x and UCC3732x family is available in the standard SOIC-8 (D) as well as the thermally enhanced -8pin PowerPAD MSOP package (DGN), drastically lowering thermal resistance to improve long term reliability. |
