Texas Instruments

The TPL5100 is a long-term timer IC optimized for low-power applications. The TPL5100 can replace a microcontroller's internal timer, allowing the microcontroller to stay completely off instead of running a timer, providing a total power consumption reduction of 60 to 80%.The TPL5100 is designed for use in power cycled applications and provides selectable timing from 16 seconds to 1024 seconds. The TPL5100 can also monitor a battery management IC via a power-good digital input and power on the microcontroller only when a good supply voltage is present. The device is packaged in a 10-pin VSSOP package. The TPL5100 is a long-term timer IC optimized for low-power applications. The TPL5100 can replace a microcontroller's internal timer, allowing the microcontroller to stay completely off instead of running a timer, providing a total power consumption reduction of 60 to 80%.The TPL5100 is designed for use in power cycled applications and provides selectable timing from 16 seconds to 1024 seconds. The TPL5100 can also monitor a battery management IC via a power-good digital input and power on the microcontroller only when a good supply voltage is present. The device is packaged in a 10-pin VSSOP package.

The TPL5110-Q1 Nano Timer is a low power, AEC-Q100 qualified timer with an integrated MOSFET driver ideal for power gating in duty cycled or battery powered applications. Consuming only 35nA, the TPL5110-Q1 can enable the power supply line and drastically reduce the overall system stand by current during the sleep time. Such power savings enable the use of significantly smaller batteries making it well suited for energy harvesting or wireless sensor applications. The TPL5110-Q1 provides selectable timing intervals from 100ms to 7200s and is designed for power gating applications. In addition, the TPL5110-Q1 has a unique One-shot feature where the timer will only power the MOSFET for one cycle. The TPL5110-Q1 is available in a 6-pin SOT23 package. The TPL5110-Q1 Nano Timer is a low power, AEC-Q100 qualified timer with an integrated MOSFET driver ideal for power gating in duty cycled or battery powered applications. Consuming only 35nA, the TPL5110-Q1 can enable the power supply line and drastically reduce the overall system stand by current during the sleep time. Such power savings enable the use of significantly smaller batteries making it well suited for energy harvesting or wireless sensor applications. The TPL5110-Q1 provides selectable timing intervals from 100ms to 7200s and is designed for power gating applications. In addition, the TPL5110-Q1 has a unique One-shot feature where the timer will only power the MOSFET for one cycle. The TPL5110-Q1 is available in a 6-pin SOT23 package.

The TPL5110-Q1 Nano Timer is a low power, AEC-Q100 qualified timer with an integrated MOSFET driver ideal for power gating in duty cycled or battery powered applications. Consuming only 35nA, the TPL5110-Q1 can enable the power supply line and drastically reduce the overall system stand by current during the sleep time. Such power savings enable the use of significantly smaller batteries making it well suited for energy harvesting or wireless sensor applications. The TPL5110-Q1 provides selectable timing intervals from 100ms to 7200s and is designed for power gating applications. In addition, the TPL5110-Q1 has a unique One-shot feature where the timer will only power the MOSFET for one cycle. The TPL5110-Q1 is available in a 6-pin SOT23 package. The TPL5110-Q1 Nano Timer is a low power, AEC-Q100 qualified timer with an integrated MOSFET driver ideal for power gating in duty cycled or battery powered applications. Consuming only 35nA, the TPL5110-Q1 can enable the power supply line and drastically reduce the overall system stand by current during the sleep time. Such power savings enable the use of significantly smaller batteries making it well suited for energy harvesting or wireless sensor applications. The TPL5110-Q1 provides selectable timing intervals from 100ms to 7200s and is designed for power gating applications. In addition, the TPL5110-Q1 has a unique One-shot feature where the timer will only power the MOSFET for one cycle. The TPL5110-Q1 is available in a 6-pin SOT23 package.

The TPL5111 Nano Timer is a low-power system timer designed for power gating in duty cycled or battery-powered applications. Consuming only 35 nA, the TPL5111 can be used to enable and disable the power supply for a micro-controller or other system device, drastically reducing the overall system stand-by current during the sleep time. This power saving enables the use of significantly smaller batteries for energy harvesting or wireless sensor applications. The TPL5111 provides selectable timing intervals from 100 ms to 7200 s. In addition, the TPL5111 has a unique one-shot feature where the timer will only assert its enable pulse for one cycle. The TPL5111 is available in a 6 -pin SOT23 package. The TPL5111 Nano Timer is a low-power system timer designed for power gating in duty cycled or battery-powered applications. Consuming only 35 nA, the TPL5111 can be used to enable and disable the power supply for a micro-controller or other system device, drastically reducing the overall system stand-by current during the sleep time. This power saving enables the use of significantly smaller batteries for energy harvesting or wireless sensor applications. The TPL5111 provides selectable timing intervals from 100 ms to 7200 s. In addition, the TPL5111 has a unique one-shot feature where the timer will only assert its enable pulse for one cycle. The TPL5111 is available in a 6 -pin SOT23 package.

The TPL7407L is a high-voltage, high-current NMOS transistor array. This device consists of seven NMOS transistors that feature high-voltage outputs with common-cathode clamp diodes for switching inductive loads. The maximum drain-current rating of a single NMOS channel is 600 mA. New regulation and drive circuitry added to give maximum drive strength across all GPIO ranges (1.8 V – 5.0 V).The transistors can be paralleled for higher current capability. The TPL7407L’s key benefit is its improved power efficiency and lower leakage than a Bipolar Darlington Implementation. With the lower VOLthe user is dissipating less than half the power than traditional relay drivers with currents less than 250 mA per channel. The TPL7407L is a high-voltage, high-current NMOS transistor array. This device consists of seven NMOS transistors that feature high-voltage outputs with common-cathode clamp diodes for switching inductive loads. The maximum drain-current rating of a single NMOS channel is 600 mA. New regulation and drive circuitry added to give maximum drive strength across all GPIO ranges (1.8 V – 5.0 V).The transistors can be paralleled for higher current capability. The TPL7407L’s key benefit is its improved power efficiency and lower leakage than a Bipolar Darlington Implementation. With the lower VOLthe user is dissipating less than half the power than traditional relay drivers with currents less than 250 mA per channel.

The TPL8002-25 is a programmable resistor device implementing two digital potentiometers with 64 wiper positions each that are tandem controlled through a 6-bit parallel interface. The device has fixed wiper resistances at the respective wiper contacts that tap the potentiometer resistors at a point determined by the binary code present at its digital inputs. The resistive wiper tap terminals, RSW, of the TPL8002-25 are typically connected to the inverting inputs (–) of an external differential path inverting operational amplifier configuration, with the non-inverting inputs (+) connected through to ground. The application’s differential input to the configuration is the device’s RG terminals. The differential output of the external operational amplifiers is connected to the device’s RF terminals, and thus becomes the differential output of the application configuration. The resistance between the wiper contacts and the end points RG and RF of the TPL8002-25 provides a logarithmic gain/attenuation response of the configuration. With a digital code of decimal 0 (b000000) the configuration has an inverting maximum attenuation of –24 dB. With a digital code of decimal 32 (b100000) the configuration has inverting unity gain of 0.00 dB. With a digital code of decimal 63 (b111111) the configuration has an inverting maximum gain of +23.25 dB. The response of the configuration with respect to the digital code varies in fixed steps of 0.75 dB. The TPL8002-25 is a programmable resistor device implementing two digital potentiometers with 64 wiper positions each that are tandem controlled through a 6-bit parallel interface. The device has fixed wiper resistances at the respective wiper contacts that tap the potentiometer resistors at a point determined by the binary code present at its digital inputs. The resistive wiper tap terminals, RSW, of the TPL8002-25 are typically connected to the inverting inputs (–) of an external differential path inverting operational amplifier configuration, with the non-inverting inputs (+) connected through to ground. The application’s differential input to the configuration is the device’s RG terminals. The differential output of the external operational amplifiers is connected to the device’s RF terminals, and thus becomes the differential output of the application configuration. The resistance between the wiper contacts and the end points RG and RF of the TPL8002-25 provides a logarithmic gain/attenuation response of the configuration. With a digital code of decimal 0 (b000000) the configuration has an inverting maximum attenuation of –24 dB. With a digital code of decimal 32 (b100000) the configuration has inverting unity gain of 0.00 dB. With a digital code of decimal 63 (b111111) the configuration has an inverting maximum gain of +23.25 dB. The response of the configuration with respect to the digital code varies in fixed steps of 0.75 dB.

The TPLD1201 is part of the TI programmable logic device (TPLD) family of devices that feature versatile programmable logic ICs with combinational logic, sequential logic, and analog blocks. TPLD provides a fully integrated, low power solution to implement common system functions, such as timing delays, voltage monitors, system resets, power sequencers, I/O expanders, and more. This device features configurable I/O structures that extends compatibility within mixed-signal environments, reducing the number of discrete components required. System designers can create circuits and configure the macro-cells, I/O pins, and interconnections by temporarily emulating the non-volatile memory or by permanently programming the one-time programmable (OTP) through InterConnect Studio. The TPLD1201 is supported by a hardware and software ecosystem with application notes, reference designs, and design examples. Visitti.comfor more information and access to design tools. The TPLD1201 is part of the TI programmable logic device (TPLD) family of devices that feature versatile programmable logic ICs with combinational logic, sequential logic, and analog blocks. TPLD provides a fully integrated, low power solution to implement common system functions, such as timing delays, voltage monitors, system resets, power sequencers, I/O expanders, and more. This device features configurable I/O structures that extends compatibility within mixed-signal environments, reducing the number of discrete components required. System designers can create circuits and configure the macro-cells, I/O pins, and interconnections by temporarily emulating the non-volatile memory or by permanently programming the one-time programmable (OTP) through InterConnect Studio. The TPLD1201 is supported by a hardware and software ecosystem with application notes, reference designs, and design examples. Visitti.comfor more information and access to design tools.

The TPPM0110 is a power source intended for use in systems that have a single 5-V input source and require dual, linearly-regulated, low-dropout voltage sources. The outputs must track within 2 V of each other during all conditions and modes of operation. Each output is protected against overcurrent conditions. In the event that one of the outputs is shorted to ground, the other output must maintain a voltage output differential of less than 2 V compared to the output with the abnormal condition. The 3.3-V ±3% regulated output is capable of driving loads of 1.5 A, and the 1.8-V ± 2% regulated output is capable of driving loads of 300 mA under all normal operating conditions. The device is available in a PowerPADTMthermally-enhanced package for efficient heat management, and requires a copper plane to dissipate the heat. The TPPM0110 is a power source intended for use in systems that have a single 5-V input source and require dual, linearly-regulated, low-dropout voltage sources. The outputs must track within 2 V of each other during all conditions and modes of operation. Each output is protected against overcurrent conditions. In the event that one of the outputs is shorted to ground, the other output must maintain a voltage output differential of less than 2 V compared to the output with the abnormal condition. The 3.3-V ±3% regulated output is capable of driving loads of 1.5 A, and the 1.8-V ± 2% regulated output is capable of driving loads of 300 mA under all normal operating conditions. The device is available in a PowerPADTMthermally-enhanced package for efficient heat management, and requires a copper plane to dissipate the heat.