Texas Instruments

The TMS320F28P65x (F28P65x) is a member of the C2000™ real-time microcontroller family of scalable, ultra-low latency devices designed for efficiency in power electronics, including but not limited to: high power density, high switching frequencies, and supporting the use of IGBT, GaN, and SiC technologies. These include such applications as: Thereal-time control subsystemis based on TI’s 32-bit C28x DSP core, which provides 200MIPS of signal-processing performance in each core for floating- or fixed-point code running from either on-chip flash or SRAM. This is equivalent to the 400MHz processing power on a Cortex®-M7 based device (C28x DSP core gives two times more performance than the Cortex®-M7 core).The C28x CPU is further boosted by theTrigonometric Math Unit (TMU)andVCRC (Cyclical Redundancy Check) extended instruction sets, speeding up common algorithms key to real-time control systems. Extended instruction sets enable IEEE double-precision 64-bit floating-point math. Finally, theControl Law Accelerator (CLA)enables an additional 200MIPS per core of independent processing ability. This is equivalent to the 280MHz processing power on a Cortex®-M7 based device (CLA CPU gives 40% more performance than the Cortex®-M7 core). The lockstep dual-CPU comparator option has been added in the secondary C28x CPU along with ePIE and DMA for detection of permanent and transient faults. To allow fast context switching from existing to new firmware, hardware enhancements for Live Firmware Update (LFU) have been added to F28P65x. High-performance analog blocks are tightly integrated with the processing and control units to provide optimal real-time signal chain performance. The Analog-to-Digital Converter (ADC) has been enhanced with up to 40 analog channels, 22 of which have general-purpose input/output (GPIO) capability. Implementation of oversampling is greatly simplified with hardware improvement. For safety-critical ADC conversions, a hardware redundancy checker has been added that provides the ability to compare ADC conversion results from multiple ADC modules for consistency without additional CPU cycles. Thirty-six frequency-independent PWMs, all with high-resolution capability, enable control of multiple power stages, from 3-phase inverters to advanced multilevel power topologies. The PWMs have been enhanced with Minimum Dead-Band Logic (MINDL) and Illegal Combo Logic (ICL) features. The inclusion of the Configurable Logic Block (CLB) allows the user to addcustom logicand potentiallyintegrate FPGA-like functionsinto the C2000 real-time MCU. An EtherCAT SubDevice Controller and other industry-standard protocols like CAN FD and USB 2.0 are available on this device. TheFast Serial Interface (FSI)enables up to 200Mbps of robust communications across an isolation boundary. As a highly connected device, the F28P65x also offers various security enablers to help designers implement their cyber security strategy and support features like hardware encryption, secure JTAG and secure Boot. From a safety standpoint, F28P65x supports numerous safety enablers. For more details, seeIndustrial Functional Safety for C2000™ Real-Time MicrocontrollersandAutomotive Functional Safety for C2000™ Real-Time Microcontrollers. Want to learn more about features that make C2000 MCUs the right choice for your real-time control system? Check outThe Essential Guide for Developing With C2000™ Real-Time Microcontrollersand visit theC2000™ real-time control MCUspage. TheGetting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guidecovers all aspects of development with C2000 devices from hardware to support resources. In addition to key reference documents, each section provides relevant links and resources to further expand on the information covered. Ready to get started? Check out theTMDSCNCD28P65Xevaluation board and downloadC2000Ware. The TMS320F28P65x (F28P65x) is a member of the C2000™ real-time microcontroller family of scalable, ultra-low latency devices designed for efficiency in power electronics, including but not limited to: high power density, high switching frequencies, and supporting the use of IGBT, GaN, and SiC technologies. These include such applications as: Thereal-time control subsystemis based on TI’s 32-bit C28x DSP core, which provides 200MIPS of signal-processing performance in each core for floating- or fixed-point code running from either on-chip flash or SRAM. This is equivalent to the 400MHz processing power on a Cortex®-M7 based device (C28x DSP core gives two times more performance than the Cortex®-M7 core).The C28x CPU is further boosted by theTrigonometric Math Unit (TMU)andVCRC (Cyclical Redundancy Check) extended instruction sets, speeding up common algorithms key to real-time control systems. Extended instruction sets enable IEEE double-precision 64-bit floating-point math. Finally, theControl Law Accelerator (CLA)enables an additional 200MIPS per core of independent processing ability. This is equivalent to the 280MHz processing power on a Cortex®-M7 based device (CLA CPU gives 40% more performance than the Cortex®-M7 core). The lockstep dual-CPU comparator option has been added in the secondary C28x CPU along with ePIE and DMA for detection of permanent and transient faults. To allow fast context switching from existing to new firmware, hardware enhancements for Live Firmware Update (LFU) have been added to F28P65x. High-performance analog blocks are tightly integrated with the processing and control units to provide optimal real-time signal chain performance. The Analog-to-Digital Converter (ADC) has been enhanced with up to 40 analog channels, 22 of which have general-purpose input/output (GPIO) capability. Implementation of oversampling is greatly simplified with hardware improvement. For safety-critical ADC conversions, a hardware redundancy checker has been added that provides the ability to compare ADC conversion results from multiple ADC modules for consistency without additional CPU cycles. Thirty-six frequency-independent PWMs, all with high-resolution capability, enable control of multiple power stages, from 3-phase inverters to advanced multilevel power topologies. The PWMs have been enhanced with Minimum Dead-Band Logic (MINDL) and Illegal Combo Logic (ICL) features. The inclusion of the Configurable Logic Block (CLB) allows the user to addcustom logicand potentiallyintegrate FPGA-like functionsinto the C2000 real-time MCU. An EtherCAT SubDevice Controller and other industry-standard protocols like CAN FD and USB 2.0 are available on this device. TheFast Serial Interface (FSI)enables up to 200Mbps of robust communications across an isolation boundary. As a highly connected device, the F28P65x also offers various security enablers to help designers implement their cyber security strategy and support features like hardware encryption, secure JTAG and secure Boot. From a safety standpoint, F28P65x supports numerous safety enablers. For more details, seeIndustrial Functional Safety for C2000™ Real-Time MicrocontrollersandAutomotive Functional Safety for C2000™ Real-Time Microcontrollers. Want to learn more about features that make C2000 MCUs the right choice for your real-time control system? Check outThe Essential Guide for Developing With C2000™ Real-Time Microcontrollersand visit theC2000™ real-time control MCUspage. TheGetting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guidecovers all aspects of development with C2000 devices from hardware to support resources. In addition to key reference documents, each section provides relevant links and resources to further expand on the information covered. Ready to get started? Check out theTMDSCNCD28P65Xevaluation board and downloadC2000Ware.

The TMS320F28P65x (F28P65x) is a member of the C2000™ real-time microcontroller family of scalable, ultra-low latency devices designed for efficiency in power electronics, including but not limited to: high power density, high switching frequencies, and supporting the use of IGBT, GaN, and SiC technologies. These include such applications as: Thereal-time control subsystemis based on TI’s 32-bit C28x DSP core, which provides 200MIPS of signal-processing performance in each core for floating- or fixed-point code running from either on-chip flash or SRAM. This is equivalent to the 400MHz processing power on a Cortex®-M7 based device (C28x DSP core gives two times more performance than the Cortex®-M7 core).The C28x CPU is further boosted by theTrigonometric Math Unit (TMU)andVCRC (Cyclical Redundancy Check) extended instruction sets, speeding up common algorithms key to real-time control systems. Extended instruction sets enable IEEE double-precision 64-bit floating-point math. Finally, theControl Law Accelerator (CLA)enables an additional 200MIPS per core of independent processing ability. This is equivalent to the 280MHz processing power on a Cortex®-M7 based device (CLA CPU gives 40% more performance than the Cortex®-M7 core). The lockstep dual-CPU comparator option has been added in the secondary C28x CPU along with ePIE and DMA for detection of permanent and transient faults. To allow fast context switching from existing to new firmware, hardware enhancements for Live Firmware Update (LFU) have been added to F28P65x. High-performance analog blocks are tightly integrated with the processing and control units to provide optimal real-time signal chain performance. The Analog-to-Digital Converter (ADC) has been enhanced with up to 40 analog channels, 22 of which have general-purpose input/output (GPIO) capability. Implementation of oversampling is greatly simplified with hardware improvement. For safety-critical ADC conversions, a hardware redundancy checker has been added that provides the ability to compare ADC conversion results from multiple ADC modules for consistency without additional CPU cycles. Thirty-six frequency-independent PWMs, all with high-resolution capability, enable control of multiple power stages, from 3-phase inverters to advanced multilevel power topologies. The PWMs have been enhanced with Minimum Dead-Band Logic (MINDL) and Illegal Combo Logic (ICL) features. The inclusion of the Configurable Logic Block (CLB) allows the user to addcustom logicand potentiallyintegrate FPGA-like functionsinto the C2000 real-time MCU. An EtherCAT SubDevice Controller and other industry-standard protocols like CAN FD and USB 2.0 are available on this device. TheFast Serial Interface (FSI)enables up to 200Mbps of robust communications across an isolation boundary. As a highly connected device, the F28P65x also offers various security enablers to help designers implement their cyber security strategy and support features like hardware encryption, secure JTAG and secure Boot. From a safety standpoint, F28P65x supports numerous safety enablers. For more details, seeIndustrial Functional Safety for C2000™ Real-Time MicrocontrollersandAutomotive Functional Safety for C2000™ Real-Time Microcontrollers. Want to learn more about features that make C2000 MCUs the right choice for your real-time control system? Check outThe Essential Guide for Developing With C2000™ Real-Time Microcontrollersand visit theC2000™ real-time control MCUspage. TheGetting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guidecovers all aspects of development with C2000 devices from hardware to support resources. In addition to key reference documents, each section provides relevant links and resources to further expand on the information covered. Ready to get started? Check out theTMDSCNCD28P65Xevaluation board and downloadC2000Ware. The TMS320F28P65x (F28P65x) is a member of the C2000™ real-time microcontroller family of scalable, ultra-low latency devices designed for efficiency in power electronics, including but not limited to: high power density, high switching frequencies, and supporting the use of IGBT, GaN, and SiC technologies. These include such applications as: Thereal-time control subsystemis based on TI’s 32-bit C28x DSP core, which provides 200MIPS of signal-processing performance in each core for floating- or fixed-point code running from either on-chip flash or SRAM. This is equivalent to the 400MHz processing power on a Cortex®-M7 based device (C28x DSP core gives two times more performance than the Cortex®-M7 core).The C28x CPU is further boosted by theTrigonometric Math Unit (TMU)andVCRC (Cyclical Redundancy Check) extended instruction sets, speeding up common algorithms key to real-time control systems. Extended instruction sets enable IEEE double-precision 64-bit floating-point math. Finally, theControl Law Accelerator (CLA)enables an additional 200MIPS per core of independent processing ability. This is equivalent to the 280MHz processing power on a Cortex®-M7 based device (CLA CPU gives 40% more performance than the Cortex®-M7 core). The lockstep dual-CPU comparator option has been added in the secondary C28x CPU along with ePIE and DMA for detection of permanent and transient faults. To allow fast context switching from existing to new firmware, hardware enhancements for Live Firmware Update (LFU) have been added to F28P65x. High-performance analog blocks are tightly integrated with the processing and control units to provide optimal real-time signal chain performance. The Analog-to-Digital Converter (ADC) has been enhanced with up to 40 analog channels, 22 of which have general-purpose input/output (GPIO) capability. Implementation of oversampling is greatly simplified with hardware improvement. For safety-critical ADC conversions, a hardware redundancy checker has been added that provides the ability to compare ADC conversion results from multiple ADC modules for consistency without additional CPU cycles. Thirty-six frequency-independent PWMs, all with high-resolution capability, enable control of multiple power stages, from 3-phase inverters to advanced multilevel power topologies. The PWMs have been enhanced with Minimum Dead-Band Logic (MINDL) and Illegal Combo Logic (ICL) features. The inclusion of the Configurable Logic Block (CLB) allows the user to addcustom logicand potentiallyintegrate FPGA-like functionsinto the C2000 real-time MCU. An EtherCAT SubDevice Controller and other industry-standard protocols like CAN FD and USB 2.0 are available on this device. TheFast Serial Interface (FSI)enables up to 200Mbps of robust communications across an isolation boundary. As a highly connected device, the F28P65x also offers various security enablers to help designers implement their cyber security strategy and support features like hardware encryption, secure JTAG and secure Boot. From a safety standpoint, F28P65x supports numerous safety enablers. For more details, seeIndustrial Functional Safety for C2000™ Real-Time MicrocontrollersandAutomotive Functional Safety for C2000™ Real-Time Microcontrollers. Want to learn more about features that make C2000 MCUs the right choice for your real-time control system? Check outThe Essential Guide for Developing With C2000™ Real-Time Microcontrollersand visit theC2000™ real-time control MCUspage. TheGetting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guidecovers all aspects of development with C2000 devices from hardware to support resources. In addition to key reference documents, each section provides relevant links and resources to further expand on the information covered. Ready to get started? Check out theTMDSCNCD28P65Xevaluation board and downloadC2000Ware.

This security RFID transponder provides an 80-bit encryption algorithm. The 5-byte challenge and 3-byte response algorithm is backward compatible with existing TI products and provides, together with the burst length coding, short encryption telegram times. The DST80 offers 65 bytes of free programmable user data stored in nine pages, each of them lockable for programming. Each of the two 80-bit encryption keys with can be programmed with a single telegram. The DST80 comes in two versions, preprogrammed with either PWM or PPM communication formats, eliminating the need for the user to change this field. For a higher security level, the DSTAES transponder with AES-128 encryption is recommended. This security RFID transponder provides an 80-bit encryption algorithm. The 5-byte challenge and 3-byte response algorithm is backward compatible with existing TI products and provides, together with the burst length coding, short encryption telegram times. The DST80 offers 65 bytes of free programmable user data stored in nine pages, each of them lockable for programming. Each of the two 80-bit encryption keys with can be programmed with a single telegram. The DST80 comes in two versions, preprogrammed with either PWM or PPM communication formats, eliminating the need for the user to change this field. For a higher security level, the DSTAES transponder with AES-128 encryption is recommended.

The TMS37157 combines a Low Frequency Transponder Interface with an SPI Interface and Power Management for a connected microcontroller. It is the ideal device for any Configuration, Data Logger-, Sensoror Remote Control Application. The Transponder memory is accessible through SPI and LF and, in the second case, operates without the need for a battery. The use of the Low Frequency Band ensures a communication in a defined direction and harsh environments. The TMS37157 manages the Transponder communication and push button interaction. During sleep state the devices enters a special low power mode with only 60 nA current consumption. The EEPROM memory is accessible over the LF interface without support from the battery or through SPI by a microcontroller if a battery is connected. The TMS37157 offers a special battery charge mode. The external resonance circuit with a LF coil and a resonance capacitor can be trimmed to the correct resonance frequency with the integrated trimming capability achieving an easy way to eliminate part tolerances. The small RSA 16-pin package together with only a few external components results in a cost efficient design. The TMS37157 combines a Low Frequency Transponder Interface with an SPI Interface and Power Management for a connected microcontroller. It is the ideal device for any Configuration, Data Logger-, Sensoror Remote Control Application. The Transponder memory is accessible through SPI and LF and, in the second case, operates without the need for a battery. The use of the Low Frequency Band ensures a communication in a defined direction and harsh environments. The TMS37157 manages the Transponder communication and push button interaction. During sleep state the devices enters a special low power mode with only 60 nA current consumption. The EEPROM memory is accessible over the LF interface without support from the battery or through SPI by a microcontroller if a battery is connected. The TMS37157 offers a special battery charge mode. The external resonance circuit with a LF coil and a resonance capacitor can be trimmed to the correct resonance frequency with the integrated trimming capability achieving an easy way to eliminate part tolerances. The small RSA 16-pin package together with only a few external components results in a cost efficient design.

The TMS470MF04207/03107 devices are members of the Texas Instruments TMS470M family of Automotive Grade 16/32-bit reduced instruction set computer (RISC) microcontrollers. The TMS470M microcontrollers offer high performance utilizing the high efficiency Cortex™-M3 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The TMS470M devices utilize the big-endian format where the most-significant byte of a word is stored at the lowest numbered byte and the least-significant byte is stored at the highest numbered byte. High-end embedded control applications demand more performance from their controllers while maintaining low costs. The TMS470M microcontroller architecture offers solutions to these performance and cost demands while maintaining low power consumption. The TMS470MF04207/03107 device contains the following: The TMS470M memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes. The SRAM on the TMS470M devices can be protected by means of ECC. This feature utilizes a single error correction and double error detection circuit (SECDED circuit) to detect and optionally correct single bit errors as well as detect all dual bit and some multi-bit errors. This is achieved by maintaining an 8-bit ECC checksum/code for each 64-bit double-word of memory space in a separate ECC RAM memory space. The flash memory on this device is a nonvolatile, electrically erasable and programmable memory. It is implemented with a 144-bit wide data word (128-bit without ECC) and a 64-bit wide flash module interface. The flash operates with a system clock frequency of up to 28 MHz. Pipeline mode, which allows linear prefetching of flash data, enables a system clock of up to 80 MHz. The enhanced real-time interrupt (RTI) module on the TMS470M devices has the option to be driven by the oscillator clock. The digital watchdog (DWD) is a 25-bit resetable decrementing counter that provides a system reset when the watchdog counter expires. The TMS470M devices have six communication interfaces: two LIN/SCIs, two DCANs, and two MibSPIs. The LIN is the Local Interconnect Network standard and also supports an SCI mode. SCI can be used in a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The DCAN uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The DCAN is ideal for applications operating in noisy and harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or multiplexed wiring. The MibSPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The MibSPI provides the standard SOMI, SIMO, and SPI clock interface as well as up to eight chip select lines. The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. The TMS470M HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high- resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET. The TMS470M devices have one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can be grouped by software for sequential conversion sequences. There are three separate groupings, all three of which can be triggered by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode. The frequency-modulated zero-pin phase-locked loop (FMzPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler. The function of the FMzPLL is to multiply the external frequency reference to a higher frequency for internal use. The FMzPLL provides the input to the global clock module (GCM). The GCM module subsequently provides system clock (HCLK), real-time interrupt clock (RTICLK), CPU clock (GCLK), HET clock (VCLK2), DCAN clock (AVCLK1), and peripheral interface clock (VCLK) to all other TMS470M device modules. The TMS470MF04207/TMS470MF03107 devices also have two external clock prescaler (ECP) modules that when enabled, output a continuous external clock (ECLK). The ECLK1 frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. The second ECLK output can be selected in place of HET15 output. It shares the same source clock as ECLK1 but can be independently programmed for a separate output frequency from ECLK1. An error signaling module (ESM) provides a common location within the device for error reporting allowing efficient error checking and identification. The TMS470MF04207/03107 devices are members of the Texas Instruments TMS470M family of Automotive Grade 16/32-bit reduced instruction set computer (RISC) microcontrollers. The TMS470M microcontrollers offer high performance utilizing the high efficiency Cortex™-M3 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The TMS470M devices utilize the big-endian format where the most-significant byte of a word is stored at the lowest numbered byte and the least-significant byte is stored at the highest numbered byte. High-end embedded control applications demand more performance from their controllers while maintaining low costs. The TMS470M microcontroller architecture offers solutions to these performance and cost demands while maintaining low power consumption. The TMS470MF04207/03107 device contains the following: The TMS470M memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes. The SRAM on the TMS470M devices can be protected by means of ECC. This feature utilizes a single error correction and double error detection circuit (SECDED circuit) to detect and optionally correct single bit errors as well as detect all dual bit and some multi-bit errors. This is achieved by maintaining an 8-bit ECC checksum/code for each 64-bit double-word of memory space in a separate ECC RAM memory space. The flash memory on this device is a nonvolatile, electrically erasable and programmable memory. It is implemented with a 144-bit wide data word (128-bit without ECC) and a 64-bit wide flash module interface. The flash operates with a system clock frequency of up to 28 MHz. Pipeline mode, which allows linear prefetching of flash data, enables a system clock of up to 80 MHz. The enhanced real-time interrupt (RTI) module on the TMS470M devices has the option to be driven by the oscillator clock. The digital watchdog (DWD) is a 25-bit resetable decrementing counter that provides a system reset when the watchdog counter expires. The TMS470M devices have six communication interfaces: two LIN/SCIs, two DCANs, and two MibSPIs. The LIN is the Local Interconnect Network standard and also supports an SCI mode. SCI can be used in a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The DCAN uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The DCAN is ideal for applications operating in noisy and harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or multiplexed wiring. The MibSPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The MibSPI provides the standard SOMI, SIMO, and SPI clock interface as well as up to eight chip select lines. The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. The TMS470M HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high- resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET. The TMS470M devices have one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can be grouped by software for sequential conversion sequences. There are three separate groupings, all three of which can be triggered by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode. The frequency-modulated zero-pin phase-locked loop (FMzPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler. The function of the FMzPLL is to multiply the external frequency reference to a higher frequency for internal use. The FMzPLL provides the input to the global clock module (GCM). The GCM module subsequently provides system clock (HCLK), real-time interrupt clock (RTICLK), CPU clock (GCLK), HET clock (VCLK2), DCAN clock (AVCLK1), and peripheral interface clock (VCLK) to all other TMS470M device modules. The TMS470MF04207/TMS470MF03107 devices also have two external clock prescaler (ECP) modules that when enabled, output a continuous external clock (ECLK). The ECLK1 frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. The second ECLK output can be selected in place of HET15 output. It shares the same source clock as ECLK1 but can be independently programmed for a separate output frequency from ECLK1. An error signaling module (ESM) provides a common location within the device for error reporting allowing efficient error checking and identification.

The TMS470R1A288(2)devices are members of the Texas Instruments TMS470R1x family of general-purpose 16/32-bit reduced instruction set computer (RISC) microcontrollers. The A288 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The A288 utilizes the big-endian format where the most significant byte of a word is stored at the lowest-numbered byte and the least significant byte at the highest numbered byte. High-end embedded control applications demand more performance from their controllers while maintaining low costs. The A288 RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption. The A288 devices contain the following: The functions performed by the 470+ system module (SYS) include: The enhanced real-time interrupt (RTI) module on the A288 has the option to be driven by the oscillator clock. The digital watchdog (DWD) is a 25-bit resettable decrementing counter that provides a system reset when the watchdog counter expires. This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see theTMS470R1x System Module Reference Guide(literature number SPNU189). The A288 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes. The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface. When in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz. The flash operates with a system clock frequency of up to 24 MHz. For more detailed information on the flash, see theFlashsection of this data sheet and theTMS470R1x F05 Flash Reference Guide(literature number SPNU213). The memory security module (MSM) and JTAG security module (JSM) prevent unauthorized access and visibility to on-chip memory, thereby preventing reverse engineering or manipulation of proprietary code. For more information, see theTMS470R1x Memory Security Module Reference Guide(literature number SPNU246) and theTMS470R1x JTAG Security Module Reference Guide(literature number SPNU245). The A288 device has ten communication interfaces: two SPIs, two SCIs, two SCCs, a C2SI, and three I2Cs. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The SCC uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating in noisy and harsh environments (e.g., industrial fields) that require reliable serial communication or multiplexed wiring. The C2SIb allows the A288 to transmit and receive messages on a class II network following an SAE J1850SAE Standard J1850 Class B Data Communication Network Interface standard. The I2C module is a multi-master communication module providing an interface between the A288 microcontroller and an I2C-compatible device via the I2C serial bus. The I2C supports both 100 Kbps and 400 Kbps speeds. For more detailed functional information on the SPI, SCI, and CAN peripherals, see the specific reference guides (literature numbers SPNU195, SPNU196, and SPNU197). For more detailed functional information on the I2C, see theTMS470R1x Inter-Integrated Circuit (I2C) Reference Guide(literature number SPNU223). For more detailed functional information on the C2SI, see theTMS470R1x Class II Serial Interface B (C2SIb) Reference Guide(literature number SPNU214). The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. The HET used in this device is the high-end timer lite. It has fewer I/Os than the usual 32 in a standard HET. For more detailed functional information on the HET, see theTMS470R1x High-End Timer (HET) Reference Guide(literature number SPNU199). The A288HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see theTMS470R1x High-End Timer (HET) Reference Guide(literature number SPNU199). The A288 device has one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. There are three separate groupings, two of which can be triggered by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode. For more detailed functional information on the MibADC, see theTMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide(literature number SPNU206). The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 1-8). The function of the ZPLL is to multiply the external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system (SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock (RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other A288 device modules. For more detailed functional information on the ZPLL, see theTMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock Module Reference Guide(literature number SPNU212). NOTE:ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system clock from an external resonator/crystal reference. The expansion bus module (EBM) is a standalone module that supports the multiplexing of the GIO functions and the expansion bus interface. For more information on the EBM, see theTMS470R1x Expansion Bus Module (EBM) Reference Guide(literature number SPNU222). The A288 device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see theTMS470R1x External Clock Prescaler (ECP) Reference Guide(literature number SPNU202). The TMS470R1A288(2)devices are members of the Texas Instruments TMS470R1x family of general-purpose 16/32-bit reduced instruction set computer (RISC) microcontrollers. The A288 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The A288 utilizes the big-endian format where the most significant byte of a word is stored at the lowest-numbered byte and the least significant byte at the highest numbered byte. High-end embedded control applications demand more performance from their controllers while maintaining low costs. The A288 RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption. The A288 devices contain the following: The functions performed by the 470+ system module (SYS) include: The enhanced real-time interrupt (RTI) module on the A288 has the option to be driven by the oscillator clock. The digital watchdog (DWD) is a 25-bit resettable decrementing counter that provides a system reset when the watchdog counter expires. This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see theTMS470R1x System Module Reference Guide(literature number SPNU189). The A288 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes. The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface. When in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz. The flash operates with a system clock frequency of up to 24 MHz. For more detailed information on the flash, see theFlashsection of this data sheet and theTMS470R1x F05 Flash Reference Guide(literature number SPNU213). The memory security module (MSM) and JTAG security module (JSM) prevent unauthorized access and visibility to on-chip memory, thereby preventing reverse engineering or manipulation of proprietary code. For more information, see theTMS470R1x Memory Security Module Reference Guide(literature number SPNU246) and theTMS470R1x JTAG Security Module Reference Guide(literature number SPNU245). The A288 device has ten communication interfaces: two SPIs, two SCIs, two SCCs, a C2SI, and three I2Cs. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The SCC uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating in noisy and harsh environments (e.g., industrial fields) that require reliable serial communication or multiplexed wiring. The C2SIb allows the A288 to transmit and receive messages on a class II network following an SAE J1850SAE Standard J1850 Class B Data Communication Network Interface standard. The I2C module is a multi-master communication module providing an interface between the A288 microcontroller and an I2C-compatible device via the I2C serial bus. The I2C supports both 100 Kbps and 400 Kbps speeds. For more detailed functional information on the SPI, SCI, and CAN peripherals, see the specific reference guides (literature numbers SPNU195, SPNU196, and SPNU197). For more detailed functional information on the I2C, see theTMS470R1x Inter-Integrated Circuit (I2C) Reference Guide(literature number SPNU223). For more detailed functional information on the C2SI, see theTMS470R1x Class II Serial Interface B (C2SIb) Reference Guide(literature number SPNU214). The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. The HET used in this device is the high-end timer lite. It has fewer I/Os than the usual 32 in a standard HET. For more detailed functional information on the HET, see theTMS470R1x High-End Timer (HET) Reference Guide(literature number SPNU199). The A288HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see theTMS470R1x High-End Timer (HET) Reference Guide(literature number SPNU199). The A288 device has one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. There are three separate groupings, two of which can be triggered by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode. For more detailed functional information on the MibADC, see theTMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide(literature number SPNU206). The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 1-8). The function of the ZPLL is to multiply the external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system (SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock (RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other A288 device modules. For more detailed functional information on the ZPLL, see theTMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock Module Reference Guide(literature number SPNU212). NOTE:ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system clock from an external resonator/crystal reference. The expansion bus module (EBM) is a standalone module that supports the multiplexing of the GIO functions and the expansion bus interface. For more information on the EBM, see theTMS470R1x Expansion Bus Module (EBM) Reference Guide(literature number SPNU222). The A288 device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see theTMS470R1x External Clock Prescaler (ECP) Reference Guide(literature number SPNU202).