Texas Instruments

The ADS5294 is a low-power 80-MSPS 8-Channel ADC that uses CMOS process technology and innovative circuit techniques. Low power consumption, high SNR, low SFDR, and consistent overload recovery allow users to design high-performance systems. The digital processing block of the ADS5294 integrates several commonly used digital functions for improving system performance. The device includes a digital filter module that has built-in decimation filters (with lowpass, highpass and bandpass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This rate is useful for narrow-band applications, where the filters are used to conveniently improve SNR and knock-off harmonics, while at the same time reducing the output data rate. The device includes an averaging mode where two channels (or even four channels) are averaged to improve SNR. Serial LVDS outputs reduce the number of interface lines and enable the highest system integration. The digital data from each channel ADC is output over one or two wires of LVDS output lines depending on the ADC sampling rate. This 2-wire interface maintains a low serial-data rate, allowing low-cost FPGA-based receivers to be used even at a high sample rate. The ADC resolution is programmed to 12-bit or 14-bit through registers. A unique feature is the programmable-mapping module that allows flexible mapping between the input channels and the LVDS output pins. This module greatly reduces the complexity of LVDS-output routing, and by reducing the number of PCB layers, potentially results in cheaper system boards. The device integrates an internal reference trimmed to accurately match across devices. Internal reference mode achieves the best performance. External references can also drive the device. The device is available in a 12-mm × 12-mm 80-pin QFP package. The device is specified over a –40°C to 85°C operating temperature range. ADS5294 is completely pin-to-pin and register compatible to ADS5292. The ADS5294 is a low-power 80-MSPS 8-Channel ADC that uses CMOS process technology and innovative circuit techniques. Low power consumption, high SNR, low SFDR, and consistent overload recovery allow users to design high-performance systems. The digital processing block of the ADS5294 integrates several commonly used digital functions for improving system performance. The device includes a digital filter module that has built-in decimation filters (with lowpass, highpass and bandpass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This rate is useful for narrow-band applications, where the filters are used to conveniently improve SNR and knock-off harmonics, while at the same time reducing the output data rate. The device includes an averaging mode where two channels (or even four channels) are averaged to improve SNR. Serial LVDS outputs reduce the number of interface lines and enable the highest system integration. The digital data from each channel ADC is output over one or two wires of LVDS output lines depending on the ADC sampling rate. This 2-wire interface maintains a low serial-data rate, allowing low-cost FPGA-based receivers to be used even at a high sample rate. The ADC resolution is programmed to 12-bit or 14-bit through registers. A unique feature is the programmable-mapping module that allows flexible mapping between the input channels and the LVDS output pins. This module greatly reduces the complexity of LVDS-output routing, and by reducing the number of PCB layers, potentially results in cheaper system boards. The device integrates an internal reference trimmed to accurately match across devices. Internal reference mode achieves the best performance. External references can also drive the device. The device is available in a 12-mm × 12-mm 80-pin QFP package. The device is specified over a –40°C to 85°C operating temperature range. ADS5294 is completely pin-to-pin and register compatible to ADS5292.

The ADS5296A is a low-power, 12-bit, 8-channel, analog-to-digital converter (ADC) with sample rates up to 80 MSPS. However, the device can also be configured to operate as a 4-channel ADC running at 2x the sample rate by interleaving data from two ADC channels. In interleaving mode, the device accepts a double frequency input clock. Each ADC in a pair converts a common analog input signal at alternate rising edges of the 2x input clock. The device can either be configured as a 10-bit, 4-channel ADC with sample rates up to 200 MSPS or as a 12-bit, 4-channel ADC with sample rates up to 160 MSPS. The data from each ADC within the interleaved pair is output in serial format over one LVDS pair up to a maximum data rate of 1 Gbps (10 bits at 100 MSPS). With interleaving disabled, the ADS5296A can also be operated as an 8-channel, 10-bit device with sample rates up to 100 MSPS. Several digital functions commonly used in systems are included in the device. These functions include a low-frequency noise suppression (LFNS) mode, digital filtering options, and programmable mapping of LVDS output pins and analog input channels. For low input frequency applications, the LFNS mode enables the suppression of noise at low frequencies and improves SNR in the 1-MHz band near dc by approximately 3 dB. Digital filtering options include low-pass, high-pass, and band-pass digital filters as well as dc offset removal filters. Low power consumption and integration of multiple channels in a small package makes the device attractive for high channel count data acquisition systems. The device is available in a compact 9-mm × 9-mm QFN-64 package. The ADS5296A is specified over the –40°C to +85°C operating temperature range. The ADS5296A is a low-power, 12-bit, 8-channel, analog-to-digital converter (ADC) with sample rates up to 80 MSPS. However, the device can also be configured to operate as a 4-channel ADC running at 2x the sample rate by interleaving data from two ADC channels. In interleaving mode, the device accepts a double frequency input clock. Each ADC in a pair converts a common analog input signal at alternate rising edges of the 2x input clock. The device can either be configured as a 10-bit, 4-channel ADC with sample rates up to 200 MSPS or as a 12-bit, 4-channel ADC with sample rates up to 160 MSPS. The data from each ADC within the interleaved pair is output in serial format over one LVDS pair up to a maximum data rate of 1 Gbps (10 bits at 100 MSPS). With interleaving disabled, the ADS5296A can also be operated as an 8-channel, 10-bit device with sample rates up to 100 MSPS. Several digital functions commonly used in systems are included in the device. These functions include a low-frequency noise suppression (LFNS) mode, digital filtering options, and programmable mapping of LVDS output pins and analog input channels. For low input frequency applications, the LFNS mode enables the suppression of noise at low frequencies and improves SNR in the 1-MHz band near dc by approximately 3 dB. Digital filtering options include low-pass, high-pass, and band-pass digital filters as well as dc offset removal filters. Low power consumption and integration of multiple channels in a small package makes the device attractive for high channel count data acquisition systems. The device is available in a compact 9-mm × 9-mm QFN-64 package. The ADS5296A is specified over the –40°C to +85°C operating temperature range.

The 8-channel, 16-bit ADS52J65 analog-to-digital converter (ADC) uses CMOS process and innovative circuit techniques. It is designed to operate at low power and give very high signal-to-noise ratio (SNR) performance with a 2-Vpp full-scale input. The device gives 80-dBFS idle SNR and 78-dBFS full-scale SNR at 5 MHz. The large input bandwidth of 250 MHz makes the device suitable for a wide range of applications, such as high frequency medical ultrasound, magnetic resonance imaging, multi-channel data acquisition, flow cytometry, flow cytometer, and hematology analyzer. The ADC integrates an internal reference trimmed to match across devices. ADS52J65 has advanced digital features, including a digital I/Q demodulator with fractional decimation filter. The ADC data from each channel is encoded using an 8B to 10B format and is sent as a SerDes data stream using current-mode logic (CML) output buffers, as per the JESD204B standard. The ADC data from all eight channels can be output over a single CML buffer (1-lane SerDes) with the data rate limited to a maximum of 12.8 Gbps. Using SerDes outputs reduces the number of interface lines. This, together with the low-power design, enables eight channels to be packaged in a 9-mm × 9-mm VQFN allowing high system integration densities. ADS52J65 also supports modes where all ADC data is sent over four CML buffers (4-Lane SerDes), reducing the SerDes data rate per lane for low-cost FPGAs. The ADS52J65 is available in a non-magnetic VQFN package that does not create any magnetic artifact. The device is specified over –40°C to +85°C. The 8-channel, 16-bit ADS52J65 analog-to-digital converter (ADC) uses CMOS process and innovative circuit techniques. It is designed to operate at low power and give very high signal-to-noise ratio (SNR) performance with a 2-Vpp full-scale input. The device gives 80-dBFS idle SNR and 78-dBFS full-scale SNR at 5 MHz. The large input bandwidth of 250 MHz makes the device suitable for a wide range of applications, such as high frequency medical ultrasound, magnetic resonance imaging, multi-channel data acquisition, flow cytometry, flow cytometer, and hematology analyzer. The ADC integrates an internal reference trimmed to match across devices. ADS52J65 has advanced digital features, including a digital I/Q demodulator with fractional decimation filter. The ADC data from each channel is encoded using an 8B to 10B format and is sent as a SerDes data stream using current-mode logic (CML) output buffers, as per the JESD204B standard. The ADC data from all eight channels can be output over a single CML buffer (1-lane SerDes) with the data rate limited to a maximum of 12.8 Gbps. Using SerDes outputs reduces the number of interface lines. This, together with the low-power design, enables eight channels to be packaged in a 9-mm × 9-mm VQFN allowing high system integration densities. ADS52J65 also supports modes where all ADC data is sent over four CML buffers (4-Lane SerDes), reducing the SerDes data rate per lane for low-cost FPGAs. The ADS52J65 is available in a non-magnetic VQFN package that does not create any magnetic artifact. The device is specified over –40°C to +85°C.

The ADS52J90 is a low-power, high-performance, 16-channel, analog-to-digital converter (ADC). The conversion rate of each ADC goes up to a maximum of 100 MSPS in 10-bit mode. The maximum conversion rate reduces when the ADC resolution is set to a higher value. The device can be configured to accept 8, 16, or 32 inputs. In 32-input mode, each ADC alternately samples and converts two different inputs each at an effective sampling rate that is half of the ADC conversion rate. In 8-bit input mode, two ADCs convert the same input in an interleaved manner, resulting in an effective sampling rate that is twice the ADC conversion rate. The ADC is designed to scale its power with the conversion rate. The ADC outputs are serialized and output through a low-voltage differential signaling (LVDS) interface along with a frame clock and a high-speed bit clock The device also has an optional JESD204B interface while operating in the 16-input and 32-input modes. This interface runs up to 5 Gbps. The ADS52J90 is available in a 9-mm × 15-mm, 0.8-mm pitch, NFBGA-198 package and is specified over a temperature range of –40°C to +85°C. The ADS52J90 is a low-power, high-performance, 16-channel, analog-to-digital converter (ADC). The conversion rate of each ADC goes up to a maximum of 100 MSPS in 10-bit mode. The maximum conversion rate reduces when the ADC resolution is set to a higher value. The device can be configured to accept 8, 16, or 32 inputs. In 32-input mode, each ADC alternately samples and converts two different inputs each at an effective sampling rate that is half of the ADC conversion rate. In 8-bit input mode, two ADCs convert the same input in an interleaved manner, resulting in an effective sampling rate that is twice the ADC conversion rate. The ADC is designed to scale its power with the conversion rate. The ADC outputs are serialized and output through a low-voltage differential signaling (LVDS) interface along with a frame clock and a high-speed bit clock The device also has an optional JESD204B interface while operating in the 16-input and 32-input modes. This interface runs up to 5 Gbps. The ADS52J90 is available in a 9-mm × 15-mm, 0.8-mm pitch, NFBGA-198 package and is specified over a temperature range of –40°C to +85°C.

The ADS5400 is a 12-bit, 1-GSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and 3.3-V supply, while providing LVDS-compatible digital outputs. The analog input buffer isolates the internal switching of the track and hold from disturbing the signal source. The simple 3-stage pipeline provides extremely low latency for time critical applications. Designed for the conversion of signals up to 2 GHz of input frequency at 1 GSPS, the ADS5400 has outstanding low noise performance and spurious-free dynamic range over a large input frequency range. The ADS5400 is available in a 100-Pin Ceramic Nonconductive Tie-Bar Package. The combination of the ceramic package and moderate power consumption of the ADS5400 allows for operation without an external heatsink. The ADS5400 is built on Texas Instrument’s complementary bipolar process (BiCom3) and is specified over the full military temperature range (–55°C to 125°C Tcase). The ADS5400 is a 12-bit, 1-GSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and 3.3-V supply, while providing LVDS-compatible digital outputs. The analog input buffer isolates the internal switching of the track and hold from disturbing the signal source. The simple 3-stage pipeline provides extremely low latency for time critical applications. Designed for the conversion of signals up to 2 GHz of input frequency at 1 GSPS, the ADS5400 has outstanding low noise performance and spurious-free dynamic range over a large input frequency range. The ADS5400 is available in a 100-Pin Ceramic Nonconductive Tie-Bar Package. The combination of the ceramic package and moderate power consumption of the ADS5400 allows for operation without an external heatsink. The ADS5400 is built on Texas Instrument’s complementary bipolar process (BiCom3) and is specified over the full military temperature range (–55°C to 125°C Tcase).