Texas Instruments

These 20-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The 'ABT16841 can be used as two 10-bit latches or one 20-bit latch. The 20 transparent D-type latches provide true data at the outputs. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (1OE\ or 2OE\) input can be used to place the outputs of the corresponding 10-bit latch in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The output-enable input does not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16841 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16841 is characterized for operation from -40°C to 85°C. These 20-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The 'ABT16841 can be used as two 10-bit latches or one 20-bit latch. The 20 transparent D-type latches provide true data at the outputs. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (1OE\ or 2OE\) input can be used to place the outputs of the corresponding 10-bit latch in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The output-enable input does not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16841 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16841 is characterized for operation from -40°C to 85°C.

The 'ABT16843 18-bit bus-interface D-type latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The 'ABT16843 can be used as two 9-bit latches or one 18-bit latch. The 18 latches are transparent D-type latches. The device provides true data at its outputs. A buffered output-enable (OE\) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs are in the high-impedance state during power up and power down. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16843 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16843 is characterized for operation from -40°C to 85°C. The 'ABT16843 18-bit bus-interface D-type latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The 'ABT16843 can be used as two 9-bit latches or one 18-bit latch. The 18 latches are transparent D-type latches. The device provides true data at its outputs. A buffered output-enable (OE\) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs are in the high-impedance state during power up and power down. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16843 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16843 is characterized for operation from -40°C to 85°C.

The 'ABT16863 are 18-bit noninverting transceivers designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements. The 'ABT16863 can be used as two 9-bit transceivers or one 18-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the output-enable (OEAB\ or OEBA\) inputs. When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16863 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16863 is characterized for operation from -40°C to 85°C. The 'ABT16863 are 18-bit noninverting transceivers designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements. The 'ABT16863 can be used as two 9-bit transceivers or one 18-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the output-enable (OEAB\ or OEBA\) inputs. When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16863 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16863 is characterized for operation from -40°C to 85°C.

The 'ABT16952 are 16-bit registered transceivers that contain two sets of D-type flip-flops for temporary storage of data flowing in either direction. The 'ABT16952 can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB\ or CLKENBA\) input is low. Taking the output-enable (OEAB\ or OEBA\) input low accesses the data on either port. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16952 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16952 is characterized for operation from -40°C to 85°C. The 'ABT16952 are 16-bit registered transceivers that contain two sets of D-type flip-flops for temporary storage of data flowing in either direction. The 'ABT16952 can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB\ or CLKENBA\) input is low. Taking the output-enable (OEAB\ or OEBA\) input low accesses the data on either port. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16952 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16952 is characterized for operation from -40°C to 85°C.

The 'ABT18245A scan test devices with 18-bit bus transceivers are members of the Texas Instruments SCOPETMtestability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, these devices are 18-bit noninverting bus transceivers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETMbus transceivers. Data flow is controlled by the direction-control (DIR) and output-enable (OE\) inputs. Data transmission is allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. OE\ can be used to disable the device so that the buses are effectively isolated. In the test mode, the normal operation of the SCOPETMbus transceivers is inhibited and the test circuitry is enabled to observe and control the input/output (I/O) boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins observe and control the operation of the test circuitry: test-data input (TDI), test-data output (TDO), test-mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. The SN54ABT18245A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT18245A is characterized for operation from -40°C to 85°C. The 'ABT18245A scan test devices with 18-bit bus transceivers are members of the Texas Instruments SCOPETMtestability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, these devices are 18-bit noninverting bus transceivers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETMbus transceivers. Data flow is controlled by the direction-control (DIR) and output-enable (OE\) inputs. Data transmission is allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. OE\ can be used to disable the device so that the buses are effectively isolated. In the test mode, the normal operation of the SCOPETMbus transceivers is inhibited and the test circuitry is enabled to observe and control the input/output (I/O) boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins observe and control the operation of the test circuitry: test-data input (TDI), test-data output (TDO), test-mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. The SN54ABT18245A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT18245A is characterized for operation from -40°C to 85°C.

The SN74ABT18502 scan test device with an 18-bit universal bus transceiver is a member of the Texas Instruments SCOPE™ testability IC family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the four-wire test access port (TAP) interface. In the normal mode, this device is an 18-bit universal bus transceiver that combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The device can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers. Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB\ is low, the B outputs are active. When OEAB\ is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow but uses the OEBA\, LEBA, and CLKBA inputs. In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary scan test operations according to the protocol described in IEEE Std 1149.1-1990. Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform other testing functions such as parallel signature analysis (PSA) on data inputs and pseudorandom pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. Additional flexibility is provided in the test mode through the use of two boundary-scan cells (BSCs) for each I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/binary count up (PSA/COUNT) instruction is also included to ease the testing of memories and other circuits where a binary count addressing scheme is useful. The SN74ABT18502 scan test device with an 18-bit universal bus transceiver is a member of the Texas Instruments SCOPE™ testability IC family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the four-wire test access port (TAP) interface. In the normal mode, this device is an 18-bit universal bus transceiver that combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The device can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers. Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB\ is low, the B outputs are active. When OEAB\ is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow but uses the OEBA\, LEBA, and CLKBA inputs. In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary scan test operations according to the protocol described in IEEE Std 1149.1-1990. Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform other testing functions such as parallel signature analysis (PSA) on data inputs and pseudorandom pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. Additional flexibility is provided in the test mode through the use of two boundary-scan cells (BSCs) for each I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/binary count up (PSA/COUNT) instruction is also included to ease the testing of memories and other circuits where a binary count addressing scheme is useful.

The SN54ABT18504 and SN74ABT18504 scan test devices with 20-bit universal bus transceivers are members of the Texas Instruments SCOPETMtestability IC family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETMuniversal bus transceivers. Data flow in each direction is controlled by output-enable (and), latch-enable (LEAB and LEBA), clock-enable (and), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched whileis high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low andis low, A-bus data is stored on a low-to-high transition of CLKAB. Whenis low, the B outputs are active. Whenis high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow but uses the, LEBA,, and CLKBA inputs. In the test mode, the normal operation of the SCOPETMuniversal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform other testing functions such as parallel signature analysis on data inputs and pseudo-random pattern generation from data outputs. All testing and scan operations are synchronized to the TAP interface. Additional flexibility is provided in the test mode through the use of two boundary scan cells (BSCs) for each I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT instruction is also included to ease the testing of memories and other circuits where a binary count addressing scheme is useful. The SN54ABT18504 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT18504 is characterized for operation from -40°C to 85°C. The SN54ABT18504 and SN74ABT18504 scan test devices with 20-bit universal bus transceivers are members of the Texas Instruments SCOPETMtestability IC family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETMuniversal bus transceivers. Data flow in each direction is controlled by output-enable (and), latch-enable (LEAB and LEBA), clock-enable (and), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched whileis high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low andis low, A-bus data is stored on a low-to-high transition of CLKAB. Whenis low, the B outputs are active. Whenis high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow but uses the, LEBA,, and CLKBA inputs. In the test mode, the normal operation of the SCOPETMuniversal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform other testing functions such as parallel signature analysis on data inputs and pseudo-random pattern generation from data outputs. All testing and scan operations are synchronized to the TAP interface. Additional flexibility is provided in the test mode through the use of two boundary scan cells (BSCs) for each I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT instruction is also included to ease the testing of memories and other circuits where a binary count addressing scheme is useful. The SN54ABT18504 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT18504 is characterized for operation from -40°C to 85°C.

The 'ABT18640 scan test devices with 18-bit inverting bus transceivers are members of the Texas Instruments SCOPETMtestability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, these devices are 18-bit inverting bus transceivers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETMbus transceivers. Data flow is controlled by the direction-control (DIR) and output-enable () inputs. Data transmission is allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR.can be used to disable the device so that the buses are effectively isolated. In the test mode, the normal operation of the SCOPETMbus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. The SN74ABT18640 is available in TI's shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN54ABT18640 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT18640 is characterized for operation from -40°C to 85°C. The 'ABT18640 scan test devices with 18-bit inverting bus transceivers are members of the Texas Instruments SCOPETMtestability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, these devices are 18-bit inverting bus transceivers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETMbus transceivers. Data flow is controlled by the direction-control (DIR) and output-enable () inputs. Data transmission is allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR.can be used to disable the device so that the buses are effectively isolated. In the test mode, the normal operation of the SCOPETMbus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. The SN74ABT18640 is available in TI's shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN54ABT18640 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT18640 is characterized for operation from -40°C to 85°C.

This scan test device with a 18-bit bus transceiver and register is a member of the Texas Instruments SCOPE™ testability IC family. This device supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the four-wire test access port (TAP) interface. In the normal mode, this device is an 18-bit bus transceiver and register that allows for multiplexed transmission of data directly from the input bus or from the internal registers. It can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE bus transceivers and registers. Transceiver function is controlled by output-enable (OE)\ and direction (DIR) inputs. When (OE)\ is low, the transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR is low. When (OE)\ is high, both the A and B outputs are in the high-impedance state, effectively isolating both buses. Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB and SAB, respectively. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74ABT18646. In the test mode, the normal operation of the SCOPE bus transceivers and registers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary scan test operations according to the protocol described in IEEE Std 1149.1-1990. Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform other testing functions, such as parallel signature analysis on data inputs and pseudorandom pattern generation from data outputs. All testing and scan operations are synchronized to the TAP interface. Additional flexibility is provided in the test mode through the use of two boundary scan cells (BSCs) for each I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT instruction is also included to ease the testing of memories and other circuits where a binary count addressing scheme is useful. This scan test device with a 18-bit bus transceiver and register is a member of the Texas Instruments SCOPE™ testability IC family. This device supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the four-wire test access port (TAP) interface. In the normal mode, this device is an 18-bit bus transceiver and register that allows for multiplexed transmission of data directly from the input bus or from the internal registers. It can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE bus transceivers and registers. Transceiver function is controlled by output-enable (OE)\ and direction (DIR) inputs. When (OE)\ is low, the transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR is low. When (OE)\ is high, both the A and B outputs are in the high-impedance state, effectively isolating both buses. Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB and SAB, respectively. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74ABT18646. In the test mode, the normal operation of the SCOPE bus transceivers and registers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary scan test operations according to the protocol described in IEEE Std 1149.1-1990. Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform other testing functions, such as parallel signature analysis on data inputs and pseudorandom pattern generation from data outputs. All testing and scan operations are synchronized to the TAP interface. Additional flexibility is provided in the test mode through the use of two boundary scan cells (BSCs) for each I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT instruction is also included to ease the testing of memories and other circuits where a binary count addressing scheme is useful.

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the 'ABT2241 and 'ABT2244A, these devices provide combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE\) inputs, and complementary OE and OE\ inputs. These devices feature high fan-out and improved fan-in. These devices are organized as two 4-bit line drivers with separate OE\ inputs. When OE\ is low, the devices pass inverted data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state. The outputs, which are designed to sink up to 12 mA, include equivalent 25-series resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT2240A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT2240A is characterized for operation from -40°C to 85°C. These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the 'ABT2241 and 'ABT2244A, these devices provide combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE\) inputs, and complementary OE and OE\ inputs. These devices feature high fan-out and improved fan-in. These devices are organized as two 4-bit line drivers with separate OE\ inputs. When OE\ is low, the devices pass inverted data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state. The outputs, which are designed to sink up to 12 mA, include equivalent 25-series resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT2240A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT2240A is characterized for operation from -40°C to 85°C.