STMicroelectronics

The STGAP2SICSN is a single gate driver which provides galvanic isolation between the gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device is available in two different configurations. The configuration with separated output pins allows to independently optimize turn-on and turn-off by using dedicated gate resistors. The configuration featuring single output pin and Miller CLAMP function prevents gate spikes during fast commutations in half-bridge topologies. Both configurations provide high flexibility and bill of material reduction for external components. The device integrates protection functions: UVLO with optimized value for SiC MOSFETs and thermal shutdown are included to easily design high reliability systems. Dual input pins allow choosing the control signal polarity and also implementing HW interlocking protection in order to avoid cross-conduction in case of controller malfunction. The input to output propagation delay results are contained within 75 ns, providing high PWM control accuracy. A standby mode is available in order to reduce idle power consumption.

The STGAP2D is a half-bridge gate driver which isolates the gate driving channels from the low voltage control and interface circuitry. The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for high power inverter applications such as motor drivers in industrial applications. The device integrates protection functions: dedicated SD and BRAKE pins are available, UVLO and thermal shutdown are included to easily design high reliability systems, and an interlocking function prevents outputs from being high at the same time. The input to output propagation delay results are contained within 75 ns, providing high PWM control accuracy. A standby mode is available in order to reduce idle power consumption.

The STGAP2GS is a single gate driver which provides galvanic isolation between the gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 2 A source and 3 A sink capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device allows to independently optimize turn-on and turn-off by using dedicated gate resistors. The device integrates protection functions including thermal shutdown and UVLO with optimized level for Enhancement-mode GaN FETs, which enables easy design high efficiency and reliable systems. Dual input pins allow the selection of signal polarity control and implementation of HW interlocking protection to avoid cross-conduction in case of controller malfunction. The input to output propagation delay results contained within 45 ns, providing high PWM control accuracy. A standby mode is available to reduce idle power consumption.

The STGAP2GSN is a single gate driver which provides isolation between the gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 2 A source and 3 A sink capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device allows to independently optimize turn-on and turn-off by using dedicated gate resistors. The device integrates protection functions including thermal shutdown ans UVLO with optimized level for Enhancement-mode GaN FETs, which enables easy design high efficiency and reliable systems. Dual input pins allow the selection of signal polarity control and implementation of HW interlocking protection to avoid cross-conduction in case of controller malfunction. The input to output propagation delay results contained within 45 ns, providing high PWM control accuracy. A standby mode is available to reduce idle power consumption.

The STGAP2HD is a dual gate driver which provides galvanic isolation between each gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 4 A current capability and rail-to-rail outputs, making it suitable for mid and high power applications such as power conversion and industrial motor driver inverters. The separated output pins allow to independently optimize turn-on and turn-off by using dedicated gate resistors, while the Miller CLAMP function allows avoiding gate spikes during fast commutations in half-bridge topologies. The device integrates protection functions: dedicated SD and BRAKE pins are available, UVLO and thermal shutdown are included to easily design high reliability systems. In half-bridge topologies the interlocking function prevents outputs from being high at the same time, avoiding shoot-through conditions in case of wrong logic input commands. The interlocking function can be disabled by a dedicated configuration pin, so to allow independent and parallel operation of the two channels. The input to output propagation delay results are contained within 75 ns, providing high PWM control accuracy. A standby mode is available in order to reduce idle power consumption.

The STGAP2HS is a single gate driver which provides galvanic isolation between the gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device is available in two different configurations. The configuration with separated output pins allows to independently optimize turn-on and turn-off by using dedicated gate resistors. The configuration featuring single output pin and Miller CLAMP function prevents gate spikes during fast commutations in half-bridge topologies. Both configurations provide high flexibility and bill of material reduction for external components. The device integrates UVLO and thermal shutdown protection functions to facilitate the design of highly reliable systems. Dual input pins allow the selection of signal polarity control and implementation of HW interlocking protection to avoid cross-conduction in case of controller malfunction. The input to output propagation delay is less than 75 ns, which delivers high PWM control accuracy. A standby mode is available to reduce idle power consumption.

The STGAP2S is a single gate driver which provides galvanic isolation between the gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device is available in two different configurations. The configuration with separated output pins allows to independently optimize turn-on and turn-off by using dedicated gate resistors. The configuration featuring single output pin and Miller CLAMP function prevents gate spikes during fast commutations in half-bridge topologies. Both configurations provide high flexibility and bill of material reduction for external components. The device integrates UVLO and thermal shutdown protection functions to facilitate the design of highly reliable systems. Dual input pins allow the selection of signal polarity control and implementation of HW interlocking protection to avoid cross-conduction in case of controller malfunction. The input to output propagation delay is less than 75 ns, which delivers high PWM control accuracy. A standby mode is available to reduce idle power consumption.

The STGAP2SiCD is a dual gate driver for SiC MOSFETs which provides galvanic isolation between each gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 4 A current capability and rail-to-rail outputs, making it suitable for mid and high power applications such as power conversion and industrial motor drivers inverters. The separated output pins allow to independently optimize turn-on and turn-off by using dedicated gate resistors, while the Miller CLAMP function allows avoiding gate spikes during fast commutations in half-bridge topologies. The device integrates protection functions: dedicated SD and BRAKE pins are available, UVLO and thermal shutdown are included to easily design high reliability systems. In half-bridge topologies the interlocking function prevents outputs from being high at the same time, avoiding shoot-through conditions in case of wrong logic input commands. The interlocking function can be disabled by a dedicated configuration pin, allowing independent and parallel operation of the two channels. The input to output propagation delay results are contained within 75 ns, providing high PWM control accuracy. A standby mode is available in order to reduce idle power consumption.

The STGAP2SICS is a single gate driver which provides galvanic isolation between the gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device is available in two different configurations. The configuration with separated output pins allows to independently optimize turn-on and turn-off by using dedicated gate resistors. The configuration featuring single output pin and Miller CLAMP function prevents gate spikes during fast commutations in half-bridge topologies. Both configurations provide high flexibility and bill of material reduction for external components. The device integrates protection functions: UVLO with optimized value for SiC MOSFETs and thermal shut down are included to facilitate the design of highly reliable systems. Dual input pins allow the selection of signal polarity control and implementation of HW interlocking protection to avoid cross-conduction in case of controller malfunction. The input to output propagation delay is less than 75 ns, which delivers high PWM control accuracy. A standby mode is available to reduce idle power consumption.

The STGAP2SICSA is a single gate driver which provides galvanic isolation between the gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device has a single output pin and Miller CLAMP function that prevents gate spikes during fast commutations in half-bridge topologies. This configuration provides high flexibility and bill of material reduction for external components. The device integrates protection functions: UVLO with optimized value for SiC MOSFETs and thermal shut down are included to facilitate the design of highly reliable systems. Dual input pins allow the selection of signal polarity control and implementation of HW interlocking protection to avoid cross-conduction in case of controller malfunction. The input to output propagation delay is less than 45 ns, which delivers high PWM control accuracy. A standby mode is available to reduce idle power consumption.