STMicroelectronics

The STM32U59xxx devices belong to an ultra-low-power microcontrollers family (STM32U5 Series) based on the high-performance Arm®Cortex®-M33 32-bit RISC core. They operate at a frequency of up to 160 MHz. The Cortex®-M33 core features a single-precision FPU (floating-point unit), that supports all the Arm®single-precision data-processing instructions and all the data types. The Cortex®-M33 core also implements a full set of DSP (digital signal processing) instructions and a MPU (memory protection unit) that enhances the application security. The devices embed high-speed memories (up to 4 Mbytes of flash memory and 2.5 Mbytes of SRAM), a FSMC (flexible external memory controller) for static memories (for devices with packages of 100 pins and more), two Octo-SPI and one Hexadeca-SPI memory interfaces (at least one Quad-SPI available on all packages) and an extensive range of enhanced I/Os and peripherals connected to three APB buses, three AHB buses and a 32-bit multi-AHB bus matrix. The devices offer security foundation compliant with the TBSA (trusted-based security architecture) requirements from Arm®. It embeds the necessary security features to implement a secure boot, secure data storage and secure firmware update. Besides these capabilities, the devices incorporate a secure firmware installation feature, that allows the customer to secure the provisioning of the code during its production. A flexible life cycle is managed thanks to multiple levels of readout protection and debug unlock with password. Firmware hardware isolation is supported thanks to securable peripherals, memories and I/Os, and privilege configuration of peripherals and memories. The devices feature several protection mechanisms for embedded flash memory and SRAM: readout protection, write protection, secure and hide protection areas. The devices embed several peripherals reinforcing security: a HASH hardware accelerator, and a true random number generator. The devices offer active tamper detection and protection against transient and environmental perturbation attacks, thanks to several internal monitoring generating secret data erase in case of attack. This helps to fit the PCI requirements for point of sales applications. The devices offer two fast 14-bit ADCs (2.5 Msps), one 12-bit ADC (2.5 Msps), two comparators, two operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, four 32-bit general-purpose timers, two 16-bit PWM timers dedicated to motor control, three 16-bit general-purpose timers, two 16-bit basic timers and four 16-bit low-power timers. The devices offer a rich set of graphic features: Neo-Chrom GPU (GPU2D) for fast texture mapping, scaling and rotation, Chrom-ART (DMA2D) for smooth motion and transparency effects, Chrom-GRC (GFXMMU) for memory optimization, MIPI®DSI Host controller with two DSI lanes running at up to 500 Mbit/s each, and LCD-TFT controller (LTDC). The devices support a MDF (multi-function digital filter) with six filters dedicated to the connection of external sigma-delta modulators. Another low-power digital filter dedicated to audio signals is embedded (ADF), with one filter supporting sound-activity detection. The devices embed mathematical accelerators (a trigonometric functions accelerator plus a filter mathematical accelerator). In addition, up to 22 capacitive sensing channels are available. The devices also feature standard and advanced communication interfaces such as: six I2Cs, three SPIs, four USARTs, two UARTs and one low-power UART, two SAIs, one DCMI (digital camera interface), two SDMMCs, one FDCAN, one USB OTG high-speed, one USB Type-C™/USB Power Delivery controller, and one generic synchronous 8-/16-bit PSSI (parallel data input/output slave interface). The devices operate in the –40 to +85 °C (+ 105 °C junction) and –40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of power-saving modes allow the design of low-power applications. Many peripherals (including communication, analog, timers and audio peripherals) can be functional and autonomous down to Stop mode with direct memory access, thanks to LPBAM support (low-power background autonomous mode). Some independent power supplies are supported like an analog independent supply input for ADC, DACs, OPAMPs and comparators, a 3.3 V dedicated supply input for USB and up to 14 I/Os, that can be supplied independently down to 1.08 V. A VBAT input is available for connecting a backup battery in order to preserve the RTC functionality and to backup 32 32-bit registers and 2-Kbyte SRAM. The devices offer ten packages from 64 to 216 pins.

The STM32U5Axxx devices belong to an ultra-low-power microcontrollers family (STM32U5 Series) based on the high-performance Arm®Cortex®-M33 32-bit RISC core. They operate at a frequency of up to 160 MHz. The Cortex®-M33 core features a single-precision FPU (floating-point unit), that supports all the Arm®single-precision data-processing instructions and all the data types. The Cortex®-M33 core also implements a full set of DSP (digital signal processing) instructions and a MPU (memory protection unit) that enhances the application security. The devices embed high-speed memories (4 Mbytes of flash memory and 2.5 Mbytes of SRAM), a FSMC (flexible external memory controller) for static memories (for devices with packages of 100 pins and more), two Octo-SPI and one Hexadeca-SPI memory interfaces (at least one Quad-SPI available on all packages) and an extensive range of enhanced I/Os and peripherals connected to three APB buses, three AHB buses and a 32-bit multi-AHB bus matrix. The devices offer security foundation compliant with the TBSA (trusted-based security architecture) requirements from Arm®. It embeds the necessary security features to implement a secure boot, secure data storage and secure firmware update. Besides these capabilities, the devices incorporate a secure firmware installation feature, that allows the customer to secure the provisioning of the code during its production. A flexible life cycle is managed thanks to multiple levels of readout protection and debug unlock with password. Firmware hardware isolation is supported thanks to securable peripherals, memories and I/Os, and privilege configuration of peripherals and memories. The devices feature several protection mechanisms for embedded flash memory and SRAM: readout protection, write protection, secure and hide protection areas. The devices embed several peripherals reinforcing security: a fast AES coprocessor, a secure AES coprocessor with DPA resistance and hardware unique key that can be shared by hardware with fast AES, a PKA (public key accelerator) with DPA resistance, an on-the-fly decryption engine for Octo-SPI external memories, a HASH hardware accelerator, and a true random number generator. The devices offer active tamper detection and protection against transient and environmental perturbation attacks, thanks to several internal monitoring generating secret data erase in case of attack. This helps to fit the PCI requirements for point of sales applications. The devices offer two fast 14-bit ADCs (2.5 Msps), one 12-bit ADC (2.5 Msps), two comparators, two operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, four 32-bit general-purpose timers, two 16-bit PWM timers dedicated to motor control, three 16-bit general-purpose timers, two 16-bit basic timers and four 16-bit low-power timers. The devices offer a rich set of graphic features: Neo-Chrom GPU (GPU2D) for fast texture mapping, scaling and rotation, Chrom-ART (DMA2D) for smooth motion and transparency effects, Chrom-GRC (GFXMMU) for memory optimization, MIPI®DSI Host controller with two DSI lanes running at up to 500 Mbit/s each, and LCD-TFT controller (LTDC). The devices support a MDF (multi-function digital filter) with six filters dedicated to the connection of external sigma-delta modulators. Another low-power digital filter dedicated to audio signals is embedded (ADF), with one filter supporting sound-activity detection. The devices embed mathematical accelerators (a trigonometric functions accelerator plus a filter mathematical accelerator). In addition, up to 22 capacitive sensing channels are available. The devices also feature standard and advanced communication interfaces such as: six I2Cs, three SPIs, four USARTs, two UARTs and one low-power UART, two SAIs, one DCMI (digital camera interface), two SDMMCs, one FDCAN, one USB OTG high-speed, one USB Type-C™/USB Power Delivery controller, and one generic synchronous 8-/16-bit PSSI (parallel data input/output slave interface). The devices operate in the –40 to +85 °C (+ 105 °C junction) and –40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of power-saving modes allow the design of low-power applications. Many peripherals (including communication, analog, timers and audio peripherals) can be functional and autonomous down to Stop mode with direct memory access, thanks to LPBAM support (low-power background autonomous mode). Some independent power supplies are supported like an analog independent supply input for ADC, DACs, OPAMPs and comparators, a 3.3 V dedicated supply input for USB and up to 14 I/Os, that can be supplied independently down to 1.08 V. A VBAT input is available for connecting a backup battery in order to preserve the RTC functionality and to backup 32 32-bit registers and 2-Kbyte SRAM. The devices offer ten packages from 64 to 216 pins.

The STM32U5Gxxx devices belong to an ultra-low-power microcontrollers family (STM32U5 Series) based on the high-performance Arm®Cortex®-M33 32-bit RISC core. They operate at a frequency of up to 160 MHz. The Cortex®-M33 core features a single-precision FPU (floating-point unit), that supports all the Arm®single-precision data-processing instructions and all the data types. The Cortex®-M33 core also implements a full set of DSP (digital signal processing) instructions and a MPU (memory protection unit) that enhances the application security. The devices embed high-speed memories (up to 4 Mbytes of flash memory and 3 Mbytes of SRAM), an FSMC (flexible external memory controller) for static memories (for devices with packages of 100 pins and more), two Octo-SPI and one Hexadeca-SPI memory interfaces (at least one Quad-SPI available on all packages) and an extensive range of enhanced I/Os and peripherals connected to three APB buses, three AHB buses and a 32-bit multi-AHB bus matrix. The devices offer security foundation compliant with the TBSA (trusted-based security architecture) requirements from Arm®. It embeds the necessary security features to implement a secure boot, secure data storage and secure firmware update. Besides these capabilities, the devices incorporate a secure firmware installation feature that allows the customer to secure the provisioning of the code during its production. A flexible life cycle is managed thanks to multiple levels of readout protection and debug unlock with password. Firmware hardware isolation is supported thanks to securable peripherals, memories and I/Os, and privilege configuration of peripherals and memories. The devices feature several protection mechanisms for embedded flash memory and SRAM: readout protection, write protection, secure and hide protection areas. The devices embed several peripherals reinforcing security: a fast AES coprocessor, a secure AES coprocessor with DPA resistance and hardware unique key that can be shared by hardware with fast AES, a PKA (public key accelerator) with DPA resistance, an on-the-fly decryption engine for Octo-SPI external memories, a HASH hardware accelerator, and a true random number generator. The devices offer active tamper detection and protection against transient and environmental perturbation attacks, thanks to several internal monitoring generating secret data erase in case of attack. This helps to fit the PCI requirements for point of sales applications. The devices offer two fast 14-bit ADCs (2.5 Msps), one 12-bit ADC (2.5 Msps), two comparators, two operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, four 32-bit general-purpose timers, two 16-bit PWM timers dedicated to motor control, three 16-bit general-purpose timers, two 16-bit basic timers and four 16-bit low-power timers. The devices offer a rich set of graphic oriented peripherals: GPU2D (Neo-Chrom graphic processor) for graphic data fast processing including vector graphic operation, DMA2D (Chrom-ART Accelerator) for enhanced graphic content creation, GFXMMU (Chrom-GRC) allowing up to 20 % of graphic resources optimization, MIPI®DSI Host controller with two DSI lanes running at up to 500 Mbit/s each, and LTDC (LCD-TFT controller), a JPEG hardware compressor/decompressor and a dedicated GFXTIM graphic timer. The devices support an MDF (multifunction digital filter) with six filters dedicated to the connection of external sigma-delta modulators. Another low-power digital filter dedicated to audio signals is embedded (ADF), with one filter supporting sound-activity detection. The devices embed mathematical accelerators (a trigonometric functions accelerator plus a filter mathematical accelerator). In addition, up to 24 capacitive sensing channels are available. The devices also feature standard and advanced communication interfaces such as: six I2Cs, three SPIs, four USARTs, two UARTs and one low-power UART, two SAIs, one DCMI (digital camera interface), two SDMMCs, one FDCAN, one USB OTG high-speed, one USB Type-C™/USB Power Delivery controller, and one generic synchronous 8-/16-bit PSSI (parallel data input/output slave interface). The devices operate in the –40 to +85 °C (+ 105 °C junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications. Many peripherals (including communication, analog, timers, and audio peripherals) can be functional and autonomous down to Stop mode with direct memory access, thanks to LPBAM support (low-power background autonomous mode). Some independent power supplies are supported like an analog independent supply input for ADC, DACs, OPAMPs and comparators, a 3.3 V dedicated supply input for USB and up to 14 I/Os that can be supplied independently down to 1.08 V. A VBAT input is available for connecting a backup battery in order to preserve the RTC functionality and to backup 32 32-bit registers and 2-Kbyte SRAM.

The STM32WBA5xxx multiprotocol wireless and ultra-low power devices embed a powerful and ultra-low power radio compliant with the Bluetooth®SIG Low Energy specification 5.4. They operate at a frequency of up to 100 MHz. The devices integrate a 2.4 GHz RADIO supporting Bluetooth Low Energy, and make possible to use proprietary protocols. The STM32WBA5xxx are based on a high-performance Arm Cortex-M33 32-bit RISC core, featuring a single-precision floating-point unit (FPU), supporting all the Arm single-precision data-processing instructions and all the data types. This core also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) that enhances the application security. The devices embed high-speed memories (up to 1 Mbyte of flash memory and up to 128 Kbytes of SRAM), an extensive range of enhanced I/Os and peripherals connected to AHB and APB buses on the 32-bit multi-AHB bus matrix. The devices offer security foundation compliant with the TBSA (trusted-based security architecture) requirements from Arm. It embeds the necessary security features to implement a secure boot, secure data storage, and secure firmware update. Besides these capabilities, the devices incorporate a secure firmware installation feature that allows the customer to secure the provisioning of the code during its production. A flexible life cycle is managed thanks to multiple levels readout protection and debug unlock with password. Firmware hardware isolation is supported thanks to securable peripherals, memories and I/Os, and privilege configuration of peripherals and memories. Several protection mechanisms are available for embedded flash memory and SRAM, namely readout and write protection, secure, and hide protection areas. The devices embed several peripherals reinforcing security: a fast AES coprocessor, a secure AES coprocessor with DPA resistance and hardware unique key that can be shared by hardware with fast AES,a PKA (public key accelerator) with DPA resistance, a HASH hardware accelerator, and a true random number generator. Active tamper detection and protection against transient perturbation attacks, is achieved thanks to several internal monitoring generating secret data erase in case of attack. This helps to fit the PCI requirements for point of sales applications. Hardware semaphores enable the synchronization between software processes. The devices offer one 12-bit ADC (2.5 Msps), two comparators, a low-power RTC, one 32-bit general-purpose timer, one 16-bit PWM timer for motor control, three 16-bit general-purpose timers, and two 16-bit low-power timers. They also feature standard and advanced communication interfaces, namely two I2Cs, two SPIs, one SAI, two USARTs, and one low-power UART. The feature set is product-dependent. The STM32WBA5xxx operate in the -40 to 105°C (120°C junction) temperature range from a 1.71 to 3.6 V power supply. The design of low-power applications is enabled by a comprehensive set of power-saving modes. Many peripherals (including radio, communication, analog, and timer peripherals) can be functional and autonomous in Stop mode with direct memory access thanks to BAM (background autonomous mode) support. Some independent power supplies are supported, like an analog independent supply input for ADC and comparators, and radio dedicated supply inputs for the 2.4 GHz RADIO. The STM32WBA5xxx devices offer three packages, up to 59 pins, with or without SMPS.

The STM32WBA5xxx multiprotocol wireless and ultra-low power devices embed a powerful and ultra-low power radio compliant with the Bluetooth®SIG Low Energy specification 5.4. They operate at a frequency of up to 100 MHz. The devices integrate a 2.4 GHz RADIO supporting Bluetooth Low Energy, and make possible to use proprietary protocols. The STM32WBA5xxx are based on a high-performance Arm Cortex-M33 32-bit RISC core, featuring a single-precision floating-point unit (FPU), supporting all the Arm single-precision data-processing instructions and all the data types. This core also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) that enhances the application security. The devices embed high-speed memories (up to 1 Mbyte of flash memory and up to 128 Kbytes of SRAM), an extensive range of enhanced I/Os and peripherals connected to AHB and APB buses on the 32-bit multi-AHB bus matrix. The devices offer security foundation compliant with the TBSA (trusted-based security architecture) requirements from Arm. It embeds the necessary security features to implement a secure boot, secure data storage, and secure firmware update. Besides these capabilities, the devices incorporate a secure firmware installation feature that allows the customer to secure the provisioning of the code during its production. A flexible life cycle is managed thanks to multiple levels readout protection and debug unlock with password. Firmware hardware isolation is supported thanks to securable peripherals, memories and I/Os, and privilege configuration of peripherals and memories. Several protection mechanisms are available for embedded flash memory and SRAM, namely readout and write protection, secure, and hide protection areas. The devices embed several peripherals reinforcing security: a fast AES coprocessor, a secure AES coprocessor with DPA resistance and hardware unique key that can be shared by hardware with fast AES,a PKA (public key accelerator) with DPA resistance, a HASH hardware accelerator, and a true random number generator. Active tamper detection and protection against transient perturbation attacks, is achieved thanks to several internal monitoring generating secret data erase in case of attack. This helps to fit the PCI requirements for point of sales applications. Hardware semaphores enable the synchronization between software processes. The devices offer one 12-bit ADC (2.5 Msps), two comparators, a low-power RTC, one 32-bit general-purpose timer, one 16-bit PWM timer for motor control, three 16-bit general-purpose timers, and two 16-bit low-power timers. They also feature standard and advanced communication interfaces, namely two I2Cs, two SPIs, one SAI, two USARTs, and one low-power UART. The feature set is product-dependent. The STM32WBA5xxx operate in the -40 to 105°C (120°C junction) temperature range from a 1.71 to 3.6 V power supply. The design of low-power applications is enabled by a comprehensive set of power-saving modes. Many peripherals (including radio, communication, analog, and timer peripherals) can be functional and autonomous in Stop mode with direct memory access thanks to BAM (background autonomous mode) support. Some independent power supplies are supported, like an analog independent supply input for ADC and comparators, and radio dedicated supply inputs for the 2.4 GHz RADIO. The STM32WBA5xxx devices offer three packages, up to 59 pins, with or without SMPS.

The STM32WL33xx is a high performance ultra-low power wireless application processor, intended for RF wireless applications in the sub-1 GHz band. It is designed to operate in both the license-free ISM and SRD frequency bands such as 433, 868, and 915 MHz. It adopts a single-core architecture embedding an Arm® 32-bit Cortex®-M0+ CPU that can operate up to 64 MHz. It integrates high-speed and flexible memory types: up to 256 Kbyte flash memory, and up to 32 Kbyte RAM, one-time programmable (OTP) memory area of 1 Kbyte. The STM32WL33xx embeds a wide set of peripherals, including a 20-pin (16 segments + 4 commons) LCD driver, 12-bit, 8 channel ADC, analog comparator, DAC, LC sensor controller, RTC, IWDG, general purpose timers, AES-128, RNG, CRC, communication interfaces such as USART, SPI, and I2C. Moreover, the security features enable secure boot with USART/SWD block (write protection) and sensitive information storage in flash (read-out protection). Direct data transfer between memory and peripherals and from memory-to-memory is supported by seven DMA channels with fully-flexible channel mapping by the DMAMUX peripheral. It can be configured to support standalone or network processor applications. In the first configuration, the STM32WL33xx operates as single device in the application for managing both the application code and proprietary sub-1 GHz protocol stacks. It operates in the -40 to +105 °C temperature range from a 1.7 V to 3.6 V power supply. A comprehensive set of power-saving modes enables the design of low-power applications. The integrated highly efficient SMPS step-down converter together with the state transition speed between low-power and active states minimize in every condition the average current consumption enabling the STM32WL33xx to be the wireless application processor most suited for battery-operated applications. The STM32WL33xx comes in different package versions supporting up to 32 I/Os for the VFQFPN48 package and 17 I/Os for the VFQFPN32 package.

The STM32WL33xx is a high performance ultra-low power wireless application processor, intended for RF wireless applications in the sub-1 GHz band. It is designed to operate in both the license-free ISM and SRD frequency bands such as 433, 868, and 915 MHz. It adopts a single-core architecture embedding an Arm® 32-bit Cortex®-M0+ CPU that can operate up to 64 MHz. It integrates high-speed and flexible memory types: up to 256 Kbyte flash memory, and up to 32 Kbyte RAM, one-time programmable (OTP) memory area of 1 Kbyte. The STM32WL33xx embeds a wide set of peripherals, including a 20-pin (16 segments + 4 commons) LCD driver, 12-bit, 8 channel ADC, analog comparator, DAC, LC sensor controller, RTC, IWDG, general purpose timers, AES-128, RNG, CRC, communication interfaces such as USART, SPI, and I2C. Moreover, the security features enable secure boot with USART/SWD block (write protection) and sensitive information storage in flash (read-out protection). Direct data transfer between memory and peripherals and from memory-to-memory is supported by seven DMA channels with fully-flexible channel mapping by the DMAMUX peripheral. It can be configured to support standalone or network processor applications. In the first configuration, the STM32WL33xx operates as single device in the application for managing both the application code and proprietary sub-1 GHz protocol stacks. It operates in the -40 to +105 °C temperature range from a 1.7 V to 3.6 V power supply. A comprehensive set of power-saving modes enables the design of low-power applications. The integrated highly efficient SMPS step-down converter together with the state transition speed between low-power and active states minimize in every condition the average current consumption enabling the STM32WL33xx to be the wireless application processor most suited for battery-operated applications. The STM32WL33xx comes in different package versions supporting up to 32 I/Os for the VFQFPN48 package and 17 I/Os for the VFQFPN32 package.

The STM6315 Microprocessor Reset Circuit is a low power supervisory device used to monitor power supplies. It performs a single function: asserting a reset signal whenever the VCCsupply voltage drops below a preset value and keeping it asserted until VCChas risen above the preset threshold for a minimum period of time (trec). It also provides a manual reset input (MR). The open drainRSToutput can be pulled up to a voltage higher than VCC, but less than 6V. The STM6315 comes with standard factory-trimmed reset thresholds of 2.63V, 2.93V, 3.08V, 4.38V, and 4.63V. The STM6315 is available in the SOT143-4 package.