Renesas Electronics Corporation

The 83026I-01 is a low skew, 1-to-2 Differential-to- LVCMOS/LVTTL Fanout Buffer. The differential input can accept most differential signal types (LVPECL, LVDS, LVHSTL, HCSL and SSTL) and translate to two single-ended LVCMOS/LVTTL outputs. The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space.

The 8302 is a low skew, 1-to-2 LVCMOS/LVTTL Fanout Buffer. The 8302 has a single-ended clock input. The single-ended clock input accepts LVCMOS or LVTTL input levels. The 8302 features a pair of LVCMOS/LVTTL outputs. The 8302 is characterized at full 3.3V for input VDD, and mixed 3.3V and 2.5V for output operating supply modes (VDDO). Guaranteed output and part-to-part skew characteristics make the 8302 ideal for clock distribution applications demanding well-defined performance and repeatability.

The 8304I is a low skew, 1-to-4 Fanout Buffer. The 8304I is characterized at full 3.3V for input VDD, and mixed 3.3V and 2.5V for output operating supply modes (VDDO). Guaranteed output and part-to-part skew characteristics make the 8304I ideal for those clock distribution applications demanding well defined performance and repeatability.

The 83052I-01 is a 2-bit, 2:1, Single-ended Multiplexer and a member of the family of High Performance Clock Solutions from IDT. The 83052I-01 has two selectable single-ended clock inputs and two single-ended clock outputs. The output has a VDDO pin which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage translation applications. An output enable pin places the output in a high impedance state which may be useful for testing or debug. Possible applications include systems with up to two transceivers which need to be independently set for different rates. For example, a board may have two transceivers, each of which need to be independently configured for 1 Gigabit Ethernet or 1 Gigabit Fibre Channel rates. Another possible application may require the ports to be independently set for FEC (Forward Error Correction) or non-FEC rates. The device operates up to 250MHz and is packaged in a 16 TSSOP.

The 83056I-01 is a 6-bit, 2:1, Single-ended LVCMOS Multiplexer and a member of the family of High Performance Clock Solutions from IDT. The 83056I-01 has two selectable single-ended LVCMOS clock inputs and six single-ended LVCMOS clock outputs. The outputs have a VDDO which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage translation applications. An output enable pin places the output in a high impedance state which may be useful for testing or debug. Possible applications include systems with up to 6 transceivers which need to be independently set for different rates. For example, a board may have six transceivers, each of which need to be independently configured for 1 Gigabit Ethernet or 1 Gigabit Fibre Channel rates. Another possible application may require the ports to be independently set for FEC (Forward Error Correction) or non-FEC rates. The device operates up to 250MHz and is packaged in a 20 TSSOP.

The 830584I is a low skew, general purpose PCI-X 1-to-4 Fanout Buffer and a member of the family of High Performance Clock Solutions from IDT. Guaranteed output and partto- part skew characteristics make the 830584I ideal for those clock distribution applications demanding well defined performance and repeatability. The 830584I is designed and characterized from -40°C to 85°C for industrial applications and is packaged in an 8 TSSOP package.

The 8305 is a low skew, 1-to-4, Differential/ LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a member of the family of High Performance Clock Solutions from IDT. The 8305 has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state. Guaranteed output and part-to-part skew characteristics make the 8305 ideal for those applications demanding well defined performance and repeatability.

The 8305I-02 is a low skew, 1-to-4, differential/LVCMOS-to-LVCMOS/LVTTL fanout buffer. The 8305I-02 has selectable clock inputs that accept either differential or single-ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/de-assertion of the clock enable pin. Outputs are forced low when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state. Guaranteed output and part-to-part skew characteristics make the 8305I-02 ideal for those applications demanding well-defined performance and repeatability.