Renesas Electronics Corporation

The 72V221 is a 1K x 9 First-In, First-Out (FIFO) memory with clocked read and write controls. It is a 3.3V version of the 72221 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks, and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronously of one another for dual clock operation.

The 72V225 is a 1K x 18 First-In, First-Out (FIFO) memory with clocked read and write controls. It is a 3.3V version of the 72225 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. The 72V225 has 18-bit input and output ports. The Read Clock (RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronously of one another for dual clock operation.

The 72V231 is a 2K x 9 First-In, First-Out (FIFO) memory with clocked read and write controls. It is a 3.3V version of the 72231 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks, and interprocessor communication. The 72V231 has 9-bit input and output ports. The Read Clock (RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronously of one another for dual clock operation.

The 72V233 2K x 9/1K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.

The 72V235 is a 2K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72235 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.

The 72V241 is a 4K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72241 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.

The 72V243 4K x 9/2K x 18 SuperSync II FIFO memory has flexible x9/x18 bus-matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes.

The 72V245 is a 4K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72245 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.

The 72V251 is an 8K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72251 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.

The 72V253 8K x 9/4K x 18 SuperSync II FIFO memory has flexible x9/x18 bus-matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes.