72V044K x 9 AsyncFIFO, 3.3V | Logic | 4 | Active | The 72V04 is a 4K x 9 dual-port First-In, First-Out (FIFO) that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. And, it has a Retransmit (RT) capability that allows for resetting the read pointer to its initial position when RT is pulsed LOW. The 72V04 is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. |
72V058K x 9 AsyncFIFO, 3.3V | Integrated Circuits (ICs) | 1 | Obsolete | The 72V05 is an 8K x 9 dual-port First-In, First-Out (FIFO) that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for resetting the read pointer to its initial position when RT is pulsed LOW. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. |
72V0616K x 9 AsyncFIFO, 3.3V | FIFOs Memory | 2 | Obsolete | The 72V06 is a 16K x 9 dual-port First-In, First-Out (FIFO) that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. And, it has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. The 72V06 is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. |
| Logic | 3 | Active | The 72V205 is a 256 x 18 First-In, First-Out (FIFO) memory with clocked read and write controls. It is a 3.3V version of the 72205 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock (RCLK) can be tied to the Write Clock (WCLK) for single clock operation or the two clocks can run asynchronously of one another for dual clock operation. |
72V2101256K x 9 SuperSync FIFO, 3.3V | Logic | 6 | Obsolete | The 72V2101 is a 256K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.) |
72V2103128K x 18 / 256K x 9 SuperSync II FIFO, 3.3V | Logic | 6 | Obsolete | The 72V2103 256K x 9/128K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes. |
72V2105256K x 18 SuperSync FIFO, 3.3V | FIFOs Memory | 4 | Active | The 72V2105 is an 256K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data. |
| Integrated Circuits (ICs) | 1 | Obsolete | The 72V211 is a 512 x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72211 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation. |
72V2113256K x 18 / 512K x 9 SuperSync II FIFO, 3.3V | FIFOs Memory | 6 | Active | The 72V2113 512K x 9/256K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes. |
| Logic | 5 | Obsolete | The 72V215 is a 512 x 18 First-In, First-Out (FIFO) memory with clocked read and write controls. It is a 3.3V version of the 72215 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock (RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronously of one another for dual clock operation. |
