Renesas Electronics Corporation

The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.)

The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 bus-matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes.

The 72V36110 128K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible bus-matching x36/x18/x9 data flow and asynchronous/synchronous translation on the read or write ports. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes.

The 72V3622 is a 3.3V version of the 723622. Two independent 256 x 36 dual-port SRAM FIFOs onboard each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

The 72V3623 is a 256 x 36 Sync FIFO that is a 3.3V version of the 723623. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. These devices can operate in the IDT Standard mode word or First Word Fall Through mode.

The 72V3631is a 512 x 36 Sync FIFO memory that is a 3.3V version of the 723631. It supports clock frequencies up to 67 MHz and has read access times as fast as 10ns. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO operates in First Word Fall Through mode. Communication between each port may take place with two 36-bit mailbox registers. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control.

The 72V3640 1K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and asynchronous/synchronous translation on the read or write ports. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes.