The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the input clock directly drives the outputs for system testing purposes. In the absence of an input clock, the 2308 enters power down, and the outputs are tri-stated. In this mode, the device will draw less than 25uA. The 2308 is available in six unique configurations for both prescaling and multiplication of the Input REF Clock. (See available options table.) The PLL is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs. The 2308 is characterized for both Industrial and Commercial operation.

The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the input clock directly drives the outputs for system testing purposes. In the absence of an input clock, the 2308A enters power down. In this mode, the device will draw less than 12uA for Commercial Temperature range and less than 25uA for Industrial temperature range, and the outputs are tri-stated. The 2308A is available in six unique configurations for both prescaling and multiplication of the Input REF Clock. (See available options table.) The PLL is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs. The 2308A is characterized for both Industrial and Commercial operation.

The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the input clock directly drives the outputs for system testing purposes. In the absence of an input clock, the 2308B enters power down, and the outputs are tri-stated. In this mode, the device will draw less than 25uA. The 2308B is available in six unique configurations for both prescaling and multiplication of the Input REF Clock. (See available options table.) The PLL is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs. The 2308B is characterized for both Industrial and Commercial operation.

The 2309 is a low phase noise, high-speed PLL based, low-skew zero delay buffer. Based on ICS' proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides nine low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The 2309 is available in two different versions. The 2309-1 is the base part. The 2309-1H is a high drive version with faster rise and fall times.

The 2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2309A is a 16-pin version of the 2305A. The 2309A accepts one reference input, and drives two banks of four low skew clocks. The -1H version of this device operates up to 133MHz frequency and has higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the 2309A enters power down. In this mode, the device will draw less than 12uA for Commercial Temperature range and less than 25uA for Industrial temperature range, and the outputs are tri-stated. The 2309A is characterized for both Industrial and Commercial operation.

The IDT2309NZ is a low-cost buffer designed to distribute high-speed clocks in mobile PC systems and desktop PC systems with SDRAM support. This part has nine outputs, eight of which can be used to drive two DIMMs or four SO-DIMMs, and the remaining can be used for external feedback to a PLL. The IDT2309NZ operates at 3.3V and outputs can run up to 133.33MHz The IDT2309NZ is designed for low EMI and power optimization. It has multiple VDD and VSS pins for noise optimization and consumes less than 32mA at 66.6MHz, making it ideal for the low power requirements of mobile systems.

2.5V Zero Delay Clock Buffer, Spread Spectrum Compatible