2305NZFive Output 3.3V Clock Buffer | Clock Buffers, Drivers | 3 | Active | The IDT2305NZ is a low-cost buffer designed to distribute high-speed clocks in mobile PC systems and desktop PC systems. The IDT2305NZ operates at 3.3V with five outputs that can run up to 133.33MHz The IDT2305NZ is an 8-pin version of the IDT2309NZ. It is designed for low EMI and power optimization and consumes less than 32mA at 66.6MHz, making it ideal for the low power requirements of mobile systems. |
| Integrated Circuits (ICs) | 1 | Active | |
| Clock Buffers, Drivers | 2 | Active | |
23083.3V Zero Delay Clock Multiplier | Clock Generators, PLLs, Frequency Synthesizers | 33 | Obsolete | The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the input clock directly drives the outputs for system testing purposes. In the absence of an input clock, the 2308 enters power down, and the outputs are tri-stated. In this mode, the device will draw less than 25uA. The 2308 is available in six unique configurations for both prescaling and multiplication of the Input REF Clock. (See available options table.) The PLL is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs. The 2308 is characterized for both Industrial and Commercial operation. |
2308-2H3.3V Zero Delay Clock Multiplier | Integrated Circuits (ICs) | 2 | Obsolete | The IDT2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the input clock directly drives the outputs for system testing purposes. In the absence of an input clock, the IDT2308 enters power down, and the outputs are tri-stated. In this mode, the device will draw less than 25μA. The IDT2308 is available in six unique configurations for both prescaling and multiplication of the Input REF Clock. (See available options table.)The PLL is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs. The IDT2308 is characterized for both Industrial and Commercial operation. |
| Clock/Timing | 21 | Active | |
| Clock Generators, PLLs, Frequency Synthesizers | 1 | Obsolete | |
| Clock/Timing | 18 | Obsolete | |
| Integrated Circuits (ICs) | 12 | Active | |
| Integrated Circuits (ICs) | 11 | Active | |
