Renesas Electronics Corporation

The 181-52 generates a low EMI output clock from a clock or crystal input. The device uses IDT's proprietary mix of analog and digital Phase Locked Loop (PLL) technology to spread the frequency spectrum of the output, thereby reducing the frequency amplitude peaks by several dB. The 181-52 offers center spread selection of +/-0.625% and +/-1.875%. Refer to the MK1714-01/02 for the widest selection of input frequencies and multipliers. IDT offers a complete line of EMI reducing clock generators. Consult us when you need to remove crystals and oscillators from your board.

The 181-51 generates a low EMI output clock from a clock or crystal input. The device uses IDT's proprietary mix of analog and digital Phase-Locked Loop (PLL) technology to spread the frequency spectrum of the output, thereby reducing the frequency amplitude peaks by several dB. The 181-51 offers center spread selection of +/-0.625% and +/-1.875%. Refer to the MK1714-01/02 for the widest selection of input frequencies and multipliers. IDT offers a complete line of EMI reducing clock generators. Consult us when you need to remove crystals and oscillators from your board.

The IDT1893Y-10 is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Col lision Detection (CSMA/CD) Ethernet standards. The IDT1893Y-10 architecture is based on the IDT1892. The IDT1893Y-10 supports managed or unmanaged node, repeater, and switch applications. The IDT1893Y-10 incorporates digital signal processing (DSP) in its Physical Medium Dependent (PMD) sublayer. As a result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cables with attenuation in excess of 24 dB at 100 MHz. With this IDT-patented technology, the IDT1893Y-10 can virtually eliminate errors from killer packets. The IDT1893Y-10 provides a Serial Management Interface for exchanging command and status information with a Station Management (STA) entity. The IDT1893Y-10 Media Dependent Interface (MDI) can be configured to provide either half- or full duplex operation at data rates of 10 MHz or 100 MHz. The MDI configuration can be established manually (with input pins or control register settings) or automatically (using the Auto-Negotiation features). When the IDT1893Y-10 Auto-Negotiation sublayer is enabled, it exchanges technology capability data with its remote link partner and automatically selects the highest-performance operating mode they have in common.

3.3-V 10Base-T/100Base-TX Integrated PHYceiver

3.3-V 10Base-T/100Base-TX Integrated PHYceiver

The 1893C is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards, ISO/IEC 8802-3. The 1893C is intended for MII, node applications that require the Auto-MDIX feature that automatically corrects crossover errors in plant wiring. The 1893C incorporates Digital-Signal Processing (DSP) control in its Physical-Medium Dependent (PMD) sublayer. As a result, it can transmit and receive data on Unshielded Twisted-Pair (UTP) Category 5 cables with attenuation in excess of 24dB at 100MHz. With this patented technology, the 1893CF can virtually eliminate errors from killer packets. The 1893C provides a Serial-Management Interface for exchanging command and status information with a Station-Management (STA) entity. The 1893C Media-Dependent Interface (MDI) can be configured to provide either half- or full-duplex operation at data rates of 10Mb/s or 100Mb/s. This device shares the same proven performance circuitry with the 1893BF and is a pin-for-pin replacement of the 1893BF.

The IDT1894-32 is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards, ISO/IEC 8802-3. The IDT1894-32 is intended for MII, Node applications that require the Auto-MDIX feature that automatically corrects crossover errors in plant wiring. The IDT1894-32 incorporates Digital-Signal Processing (DSP) control in its Physical-Medium Dependent (PMD) sub layer. As a result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cables with attenuation in excess of 24 dB at 100MHz. With this IDT-patented technology, the IDT1894-32 can virtually eliminate errors from killer packets. The IDT1894-32 provides a Serial-Management Interface for exchanging command and status information with a Station-Management (STA) entity. The IDT1894-32 Media-Dependent Interface (MDI) can be configured to provide either half- or full duplex operation at data rates of 10 Mb/s or 100Mb/s. In addition, the IDT1894-32 includes a programmable interrupt output function. This function consists of a digital output pin, an interrupt control register, a set of interrupt status register bits and a corresponding set of interrupt enable bits, and a pre-defined set of events which can be assigned as one of the interrupt sources. The purpose of this function is to notify the host of this PHY device when certain event happens via interrupt (the logic level on interrupt output pin going low or going high) instead of polling by the host. The events that could be used to generate interrupts are: receiver error, Jabber, page received, parallel detect fault, link partner acknowledge, link status change, auto-negotiation complete, remote fault, collision, etc.Applications: NIC cards, PC motherboards, switches, routers, DSL and cable modems, game machines, printers, network connected appliances, and industrial equipment.