557-062 to 4 Differential PCIe GEN1 Clock MUX | Clock/Timing | 3 | Active | The 557-06 is a two to four differential clock mux designed for use in PCI-Express applications. The device selects one of the two differential HCSL input pairs and fans out to four pairs of differential HCSL or LVDS outputs. |
557-082:1 Multiplexer Chip For PCI-Express GEN1 | Clock/Timing | 3 | Obsolete | The 557-08 is a 2:1 multiplexer chip that allows the user to select one of the two HCSL (Host Clock Signal Level) input pairs and fans out to one pair of differential HCSL or LVDS outputs. This chip is suited especially for PCI-Express applications, where there is a need to select the PCI-Express clock either locally from the PCI-E card or from the motherboard. |
557G2:1 Multiplexer Chip For PCI-Express GEN1 | Application Specific | 5 | Active | The 557-05A is a spread-spectrum clock generator that supports PCI-Express requirements. It is used in PC or embedded systems to substantially reduce electro-magnetic interference (EMI). The device provides four differential HCSL or LVDS high-frequency outputs with spread spectrum capability. The output frequency and spread type are selectable using external pins. |
558-01PECL/CMOS to CMOS Clock Driver | Clock/Timing | 2 | Obsolete | The 558-01 accepts a high speed input of either PECL or CMOS, integrates a divider of 1, 2, 3, or 4, and provides four CMOS low skew outputs. The chip also has output enables so that one, three, or all four outputs can be tri-stated. The 558-01 is a member of the IDT Clock Blocks™ family of clock generation, synchronization, and distribution devices. |
570Multiplier and Zero Delay Buffer | Clock/Timing | 8 | Active | The IDT570 is a high-performance Zero Delay Buffer (ZDB) which integrates IDT's proprietary analog/digital Phase Locked Loop (PLL) techniques. The A version is recommended for 5 V designs and the B version for 3.3 V designs. The chip is part of IDT's ClockBlocks™ family, and was designed as a performance upgrade to meet today's higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both output clocks, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other output. The device incorporates an all-chip power down/tri-state mode that stops the internal PLL and puts both outputs into a high impedance state. The IDT570 is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to graphIDT/video. By allowing off-chip feedback paths, the device can eliminate the delay through other devices. |
571Low Phase Noise Zero Delay Buffer | Integrated Circuits (ICs) | 1 | Obsolete | The 571 is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates IDT's proprietary analog/digital Phase Locked Loop (PLL) techniques. IDT introduced the world standard for these devices in 1992 with the debut of the AV9170, and updated that with the 570. The 571, part of IDT's ClockBlocks™ family, was designed to operate at higher frequencies, with faster rise and fall times, and with lower phase noise. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both outputs, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other. The chip is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to video. By allowing offchip feedback paths, the 571 can eliminate the delay through other devices. The use of dividers in the feedback path will enable the part to multiply by more than two. |
571MLow Phase Noise Zero Delay Buffer | Integrated Circuits (ICs) | 1 | Obsolete | The 571 is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates IDT's proprietary analog/digital Phase Locked Loop (PLL) techniques. IDT introduced the world standard for these devices in 1992 with the debut of the AV9170, and updated that with the 570. The 571, part of IDT's ClockBlocks™ family, was designed to operate at higher frequencies, with faster rise and fall times, and with lower phase noise. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both outputs, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other. The chip is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to video. By allowing offchip feedback paths, the 571 can eliminate the delay through other devices. The use of dividers in the feedback path will enable the part to multiply by more than two. |
574Zero Delay, Low Skew Buffer | Clock Generators, PLLs, Frequency Synthesizers | 4 | Obsolete | The 574 is a low jitter, low-skew, high performance PLL-based zero delay buffer for high speed applications. Based on IDT's proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 160 MHz at 3.3 V. When one of the outputs is connected directly to FBIN, the rising edge of each output is aligned with the rising edge of the input clock. External delay elements connected in the feedback loops will cause the outputs to occur before the inputs by the amount of propagation delay of the external element. |
| Integrated Circuits (ICs) | 6 | Obsolete | |
| Clock Generators, PLLs, Frequency Synthesizers | 4 | Obsolete | |
