| Logic | 2 | Active | |
| Integrated Circuits (ICs) | 5 | Active | The HEF4013B-Q100 is a dual D-type flip-flop with set and reset; positive-edge trigger. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. Schmitt-trigger action on the clock input makes the circuit highly tolerant of slower clock rise and fall times. |
| Integrated Circuits (ICs) | 3 | Active | The HEF4014B is an 8-bit shift register with synchronous parallel enable. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. |
| Shift Registers | 1 | Active | |
| Analog Switches, Multiplexers, Demultiplexers | 1 | Obsolete | |
| Counters, Dividers | 2 | Active | |
| Logic | 3 | Active | The HEF40175B is a quad positive edge triggered D-type flip-flop with four data (Dn) inputs, common clock (CP) and asynchronous master reset (MR) inputs, and complementary Qn andQn outputs. WhenMRis HIGH data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. When LOW,MRresets all flip-flops (Qn = LOW,Qn = HIGH), independent of CP and Dn. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. |
| Flip Flops | 1 | Active | The HEF40175B-Q100 is a quad positive edge triggered D-type flip-flop with four data (Dn) inputs, common clock (CP) and asynchronous master reset (MR) inputs, and complementary Qn andQn outputs. WhenMRis HIGH data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. When LOW,MRresets all flip-flops (Qn = LOW,Qn = HIGH), independent of CP and Dn. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. |
| Logic | 1 | Active | TheHEF4017Bis a5-stage Johnson decade counterwith ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q5-9), active HIGH and active LOW clock inputs (CP0,CP1) and an overriding asynchronous master reset input (MR). |
| Logic | 1 | Active | TheHEF4021B-Q100is an8-bit static shift register(parallel-to-serial converter). It has a synchronous serial data input (DS), a clock input (CP) and an asynchronous active HIGH parallel load input (PL). TheHEF4021B-Q100also has eight asynchronous parallel data inputs (D0 to D7) and buffered parallel outputs from the last three stages (Q5 to Q7). Each register stage is a D-type master-slave flip-flop with a set direct (SD) and clear direct (CD) input. Information on D0 to D7 is asynchronously loaded into the register while PL is HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first register position. All the data in the register is shifted one position to the right on the LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times. |
