| Shift Registers | 1 | Active | The HEF4021B is an 8-bit static shift register (parallel-to-serial converter) with a synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH parallel load input (PL), eight asynchronous parallel data inputs (D0 to D7) and buffered parallel outputs from the last three stages (Q5 to Q7). Each register stage is a D-type master-slave flip-flop with a set direct (SD) and clear direct (CD) input. Information on D0 to D7 is asynchronously loaded into the register while PL is HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first register position and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times. |
| Logic | 1 | Active | TheHEF4021B-Q100is an8-bit static shift register(parallel-to-serial converter). It has a synchronous serial data input (DS), a clock input (CP) and an asynchronous active HIGH parallel load input (PL). TheHEF4021B-Q100also has eight asynchronous parallel data inputs (D0 to D7) and buffered parallel outputs from the last three stages (Q5 to Q7). Each register stage is a D-type master-slave flip-flop with a set direct (SD) and clear direct (CD) input. Information on D0 to D7 is asynchronously loaded into the register while PL is HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first register position. All the data in the register is shifted one position to the right on the LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times. |
HEF40244Octal buffers with 3-state outputs | Integrated Circuits (ICs) | 2 | Active | The HEF40244B is an 8-bit buffer/line driver with 3-state outputs. The device can be used as two 4-bit buffers or one 8-bit buffer. The device features two output enables (1OEand 2OE), each controlling four of the 3-state outputs. A HIGH on nOEcauses the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
| Buffers, Drivers, Receivers, Transceivers | 1 | Active | The HEF40244B-Q100 is an 8-bit buffer/line driver with 3-state outputs. The device can be used as two 4-bit buffers or one 8-bit buffer. The device features two output enables (1OEand 2OE), each controlling four of the 3-state outputs. A HIGH on nOEcauses the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
| Logic | 3 | Active | The HEF4027B is a dual positive-edge triggered JK flip-flop featuring independent set direct (nSD), clear direct (nCD), clock inputs (nCP) and complementary outputs (nQ and nQ). Data is accepted when nCP is LOW, and transferred to the output on the positive-going edge of the clock. The asynchronous clear-direct (nCD) and set-direct (nSD) are independent and override the nJ, nK, and nCP inputs. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. |
| Logic | 2 | Active | The HEF4028B is a 4-bit BCD to 1-of-10 decoder. A 1-2-4-8 BCD code applied to inputs A0 to A3 causes the selected output to be HIGH, the other nine will be LOW. To use as a 1-of-8 decoder with enable, 3-bit octal inputs are applied to inputs A0 , A1 and A2 selecting an output Y0 to Y7 . Input A3 then becomes an active LOW enable, forcing the selected output LOW when A3 is HIGH. The device may also be used as an 8-output (Y0 to Y7) demultiplexer with A0 to A2 as address inputs and A3 as an active LOW data input. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. |
| Logic | 1 | Active | |
| Integrated Circuits (ICs) | 1 | Obsolete | |
HEF404012-stage binary ripple counter | Integrated Circuits (ICs) | 2 | Active | TheHEF4040Bis a12-stage binary ripple counterwith a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition ofCP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent ofCP. Each counter stage is a static toggle flip-flop. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications. |
| Integrated Circuits (ICs) | 2 | Active | |
