HEF40175BT Series

Quad D-type flip-flop

Manufacturer: Freescale Semiconductor - NXP

Catalog

Quad D-type flip-flop

Part	Mounting Type	Trigger Type	Package / Case	Package / Case [x]	Package / Case [y]	Number of Elements	Number of Bits per Element	Output Type	Operating Temperature [Min]	Operating Temperature [Max]	Current - Quiescent (Iq)	Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Clock Frequency	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Supplier Device Package	Input Capacitance	Max Propagation Delay @ V, Max CL
Freescale Semiconductor - NXP HEF40175BT,652	Surface Mount	Positive Edge	16-SOIC	0.154 in	3.9 mm	1	4	Complementary	-40 °C	125 °C	4 çA	D-Type	15 V	3 V	45 MHz	3.4 mA	3.4 mA	16-SO	7.5 pF
Freescale Semiconductor - NXP HEF40175BT,653	Surface Mount	Positive Edge	16-SOIC	0.154 in	3.9 mm	1	4	Complementary	-40 °C	125 °C	4 çA	D-Type	15 V	3 V	45 MHz	3.4 mA	3.4 mA	16-SO	7.5 pF	45 ns
Freescale Semiconductor - NXP HEF40175BTT,118	Surface Mount	Positive Edge	16-TSSOP	0.173 in	4.4 mm	1	4	Complementary	-40 °C	125 °C	4 çA	D-Type	15 V	3 V	45 MHz	3.4 mA	3.4 mA	16-TSSOP	7.5 pF	45 ns

Catalog

Quad D-type flip-flop

Key Features

• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

Description

The HEF40175B is a quad positive edge triggered D-type flip-flop with four data (Dn) inputs, common clock (CP) and asynchronous master reset (MR) inputs, and complementary Qn andQn outputs. WhenMRis HIGH data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. When LOW,MRresets all flip-flops (Qn = LOW,Qn = HIGH), independent of CP and Dn. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD.