74LV138D-Q100 Series

The 74LV138-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 toY7). The 74LV138-Q100 features three enable inputs (Y1,Y2 and E3). Every output will be HIGH unlessY1 andY2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the 74LV138-Q100 to a 1-of-32 (5 to 32 lines) decoder with just four 74LV138 ICs and one inverter. The 74LV138-Q100 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC.