Microchip Technology

The SY89202U is a precision, high-speed, integrated clock divider LVPECL fanout buffer capable of handling clocks up to 1.5GHz. Optimized for communications applications, the three independently controlled output banks are phase matched and can be configured for pass-through (÷1), ÷2 or ÷4 divide ratios.The differential input includes Micrel's unique, 3-pin input termination architecture that allows the user to interface to any AC- or DC-coupled signal as small as 100mV (200mVpp) without any level shifting or termination resistor networks in the signal path. The low skew, low jitter outputs are 800mV, 100k compatible LVPECL, with extremely fast rise/fall times guaranteed to be less than 220ps.The EN (enable) input guarantees that the ÷1, ÷2 and ÷4 outputs will start from the same state without any runt pulse after an asynchronous MR (master reset) is asserted. This is accomplished by enabling the outputs after a four-clock delay to allow the counters to synchronize.The SY89202U is part of Micrel's Precision Edge® product family.

The SY89218U is a 2.5V precision, high-speed, integrated clock divider and LVDS fanout buffer capable of handling clocks up to 1.5GHz. Optimized for communications applications, the four independently controlled output banks are phase-matched and can be configured for pass through (÷1), ÷2 or ÷4 divider ratios.The differential input includes Micrel's unique, 3-pin input termination architecture that allows the user to interface to any differential signal (AC- or DC-coupled) as small as 100mV (200mVPP) without any level shifting or termination resistor networks in the signal path. The low-skew, low-jitter outputs are LVDS compatible with extremely fast rise/fall times guaranteed to be less than 200ps.The /MR (master reset) input asynchronously resets the outputs. A four-clock delay after de-asserting /MR allows the counters to synchronize and start the outputs from the same state without any runt pulse.The SY89218U is part of Micrel's Precision Edge® product family.

The SY89221U is a 2.5/3.3V precision, high-speed, integrated clock divider and LVPECL fanout buffer capable of handling clocks up to 1.5GHz. Optimized for communications applications, the four independently controlled output banks are phasematched and can be configured for pass through ÷1, ÷2 or ÷4 divider ratios.The differential input includes Micrel's unique, 3-pin input termination architecture that allows the user to interface to any differential signal (AC- or DC-coupled) as small as 100mV (200mVPP) without any level shifting or termination resistor networks in the signal path. The low-skew, low-jitter outputs are LVPECL compatible with extremely fast rise/fall times that are guaranteed to be less than 220ps.The /MR (master reset) input asynchronously resets the outputs. A four-clock delay after de-asserting /MR allows the counters to synchronize and start the outputs from the same state without any runt pulse.The SY89221U is part of Micrel's Precision Edge® product family.

The SY89222L is a dual TTL-to-differential LVPECL translator with a +3.3V power supply. Because LVPECL (Positive ECL) levels are used, only +3.3V and ground are required. The SY89222L is functionally equivalent to the SY100ELT22L but in an ultra-small 8-lead MLF™ package that features a 70% smaller footprint. The low skew, dual gate design of the SY89222L makes it ideal for applications that require the translation of a clock and a data signal.

The SY89250V is a differential PECL/ECL receiver/buffer in a space saving (2mm x 2mm) MLF® package. The device is functionally equivalent to the SY100EL16VC, but features a 70% smaller footprint. It provides a VBB output for either single-ended application or as a DC bias for AC-coupling to the device.The SY89250V provides an /EN input which is synchronized with the data input (D) signal in a way that provides glitchless gating of the QHG and /QHG outputs. When the /EN signal is LOW, the input is passed to the outputs and the data output equals the data input. When the data input is HIGH and the /EN goes HIGH, it will force the QHG LOW and the /QHG HIGH on the next negative transition of the data input. If the data input is LOW when the /EN goes HIGH, the next data transition to a HIGH is ignored and QHG remains LOW and /QHG remains HIGH. The next positive transition of the data input is not passed on to the data outputs under these conditions. The QHG and /QHG outputs remain in their disabled state as long as the /EN input is held HIGH. The /EN input has no influence on the /Q output and the data input is passed on (inverted) to this output whether /EN is HIGH or LOW. This configuration is ideal for crystal oscillator applications, where the oscillator can be free running and gated on and off synchronously without adding extra counts to the output.