Microchip Technology

The SY89251V is a differential PECL/ECL receiver/buffer in a space saving (2mm x 2mm) DFN package. The device is functionally equivalent to the SY100EL16VC, except for an active HIGH enable pin and a 70% smaller footprint. It is also equivalent to the SY89250V, except for an active HIGH enable pin. It provides a VBB output for either single-ended application or as a DC bias for AC-coupling to the device.The SY89251V provides an EN input which is synchronized with the data input (D) signal in a way that provides glitchless gating of the QHG and /QHG outputs. When the EN signal is HIGH, the input is passed to the outputs and the data output equals the data input. When the data input is HIGH and the EN goes LOW, it will force the QHG LOW and the /QHG HIGH on the next negative transition of the data input. If the data input is LOW when the EN goes LOW, the next data transition to a HIGH is ignored and QHG remains LOW and /QHG remains HIGH. The next positive transition of the data input is not passed on to the data outputs under these conditions. The QHG and /QHG outputs remain in their disabled state as long as the EN input is held LOW. The EN input has no influence on the /Q output and the data input is passed on (inverted) to this output whether EN is HIGH or LOW. This configuration is ideal for crystal oscillator applications, where the oscillator can be free running and gated on and off synchronously without adding extra counts to the output.

The SY89295U is a programmable delay line that delays the input signal using a digital control signal. The delay can vary from 3.2ns to 14.8ns in 10ps increments. In addition, the input signal is LVPECL, uses either a 2.5V ±5% or 3.3V ±10% power supply, and is guaranteed over the full industrial temperature range (-40°C to +85°C).The delay varies in discrete steps based on a control word. The control word is 10-bits long and controls the delay in 10ps increments. The eleventh bit is D[10] and is used to simultaneously cascade the SY89295U which allows for a larger delay range. In addition, the input pins IN and /IN default to an equivalent low state when left floating. Further, for maximum flexibility, the control register interface accepts CMOS or TTL level signals.For applications that require an analog delay input, see the SY89296L which is a programmable delay chip with fine tune control. The SY89295U and SY89296U are part of Micrel's high-speed, Precision Edge® product line.

The SY89297U is a DC-3.2Gbps programmable, two-channel delay line. Each channel has a delay range from 2ns to 7ns (5ns delta delay) in programmable increments as small as 5ps. The delay step is extremely linear and monotonic over the entire programming range, with 15ps INL over temperature and voltage.The delay varies in discrete steps based on a serial control word provided by the 3-pin serial control (SDATA, SCLK, and SLOAD). The control word for each channel is 10-bits. Both channels are programmed through a common serial interface. For increased delay, multiple SY89297U delay lines can be cascaded together.The SY89297U provides two independent 3.2Gbps delay lines in an ultra-small 4mm x 4mm, 24-pin QFN package. For other delay line solutions, consider the SY89295U and SY89296U single-channel delay lines. Evaluation boards are available for all these parts.

The SY89306V and SY89316V are a high-speed buffer/ receivers. The devices are functionally equivalent to the 10/100EP16 buffers, but feature a 70% smaller footprint.The SY89306/316V includes a VBB reference for singleended AC-coupling applications. Whenever used, the VBB pin should be bypassed to ground via a 0.01µF capacitor. VBB reference can only sink/source 0.5mA. Under open input conditions (pulled to VEE), internal input clamps will force the Q output LOW.

The SY89311U is a precision, high-speed 1:2 differential fanout buffer. Having within-device skews and output transition times significantly improved over the EL11V, the SY89311U is ideally suited for those applications which require the ultimate in AC performance in a small package.The differential inputs of the SY89311U employ clamping circuitry to maintain stability under open input conditions. If the inputs are left open, the Q outputs will be LOW.The differential inputs can accept 10/100K ECL/PECL signals (external termination required) and the outputs are 100K ECL/PECL compatible..

The SY89313V is a differential ECL/PECL integrated ÷4 divider clock generator. It is functionally equivalent to the SY100EP33V but in an ultra-small 8-lead MLF® package that features a 70% smaller footprint.The VBB pin, an internally generated voltage supply, is available for this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also re-bias ACcoupled inputs. When used, decouple VBB and VCC via a 0.01µF capacitor and limit current sourcing or sinking to 0.5mA. When not used, VBB should be left open.The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will be in a random state; the reset allows for the synchronous use of multiple SY89313V's in a system.