| RF Misc ICs and Modules | 1 | Active | The AD6672 is an 11-bit intermediate receiver with sampling speeds of up to 250 MSPS. The AD6672 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.The ADC core output is connected internally to a noise shaping requantizer (NSR) block. The device supports two output modes that are selectable via the serial port interface (SPI). With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6672 supports enhanced SNR performance within a limited region of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block is programmed to provide a bandwidth of up to 33% of the sample clock. For example, with a sample clock rate of 250 MSPS, the AD6672 can achieve up to 73.6 dBFS SNR for an 82 MHz bandwidth at 185 MHz fIN.With the NSR block disabled, the ADC data is provided directly to the output with an output resolution of 11 bits. The AD6672 can achieve up to 66.6 dBFS SNR for the entire Nyquist bandwidth when operated in this mode.APPLICATIONSCommunicationsDiversity radio and smart antenna (MIMO) systemsMultimode digital receivers (3G)WCDMA, LTE, CDMA2000WiMAX, TD-SCDMAI/Q demodulation systemsGeneral-purpose software radios |
AD667380 MHzBandwidth, Dual IF Receiver | RF, RFID, Wireless Evaluation Boards | 3 | Active | The AD6673 is an 11-bit, 250 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic, and each ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the SPI. With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6673 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution.The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 250 MSPS, the AD6673 can achieve up to 76.3 dBFS SNR for a 55 MHz bandwidth in the 22% mode and up to 73.5 dBFS SNR for a 82 MHz bandwidth in the 33% mode.When the NSR block is disabled, the ADC data is provided directly to the output at a resolution of 11 bits. The AD6673 can achieve up to 65.9 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6673 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are required.By default the ADC output data is routed directly to the two external JESD204B serial output lanes. These outputs are at current mode logic (CML) voltage levels. Two modes are supported such that output coded data is either sent through one lane or two (L = 1; F = 4 or L = 2; F = 2). Single lane operation supports converter rates up to 125 MSPS. Synchronization input controls (SYNCINB± and SYSREF±) are provided.PRODUCT HIGHLIGHTSThe configurable JESD204B output block with an integrated phase-locked loop (PLL) to support up to 5 Gbps per lane with up to two lanes.IF receiver includes two, 11-bit, 250 MSPS ADCs with programmable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of 22% or 33% of the sample rate.Support for an optional RF clock input to ease system board design.Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz.An on-chip integer, 1-to-8 input clock divider and SYNC input allows synchronization of multiple devices.Operation from a single 1.8 V power supply.Standard serial port interface (SPI) that supports various product features and functions, such as controlling the clock DCS, power-down, test modes, voltage reference mode, overrange fast detection, and serial output configuration.APPLICATIONSCommunicationsDiversity radio and smart antenna (MIMO) systemsMultimode digital receivers (3G)TD-SCDMA, WiMAX, WCDMA, CDMA2000, GSM, EDGE, LTEI/Q demodulation systemsGeneral-purpose software radios |
AD6674385 MHz BW IF Diversity Receiver | RF, RFID, Wireless Evaluation Boards | 8 | Active | The AD6674 is a 385 MHz bandwidth mixed-signal intermediate frequency (IF) receiver. It consists of two, 14-bit 1.0 GSPS/750 MSPS/500 MSPS analog-to-digital converters (ADC) and various digital signal processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz. The AD6674 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.ApplicationsDiversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-ADOCSIS 3.0 CMTS upstream receive pathsHFC digital reverse path receivers |
| RF Misc ICs and Modules | 2 | Active | |
| RF Misc ICs and Modules | 3 | Active | |
AD669Monolithic 16-Bit DACPORT | Integrated Circuits (ICs) | 8 | Active | The AD669 DACPORT®is a complete 16-bit monolithic D/A converter with an on-board reference and output amplifier. It is manufactured on Analog Devices' BiMOS II process. This process allows the fabrication of low power CMOS logic functions on the same chip as high precision bipolar linear circuitry. The AD669 chip includes current switches, decoding logic, an output amplifier, a buried Zener reference and double-buffered latches.The AD669's architecture insures 15-bit monotonicity over temperature. Integral nonlinearity is maintained at ±0.003%, while differential nonlinearity is ±0.003% max. The on-chip output amplifier provides a voltage output settling time of 10 ms to within 1/2 LSB for a full-scale step.Data is loaded into the AD669 in a parallel 16-bit format. The double-buffered latch structure eliminates data skew errors and provides for simultaneous updating of DACs in a multi-DAC system. Three TTL/LSTTL/5 V CMOS compatible signals control the latches:CS,L1andLDAC.The output range of the AD669 is pin programmable and can be set to provide a unipolar output range of 0 V to +10 V or a bipolar output range of -10 V to +10 V.The AD669 is available in seven grades: AN and BN versions are specified from -40°C to +85°C and are packaged in a 28-pin plastic DIP. The AR and BR versions are specified for -40°C to +85°C operation and are packaged in a 28-pin SOIC. The SQ version is specified from -55°C to +125°C and is packaged in a hermetic 28-pin cerdip package. The AD669 is also available compliant to MIL-STD-883. Refer to the AD669/883B data sheet for specifications and test conditions.PRODUCT HIGHLIGHTSThe AD669 is a complete voltage output 16-bit DAC with voltage reference and digital latches on a single IC chip.The internal buried Zener reference is laser trimmed to 10.000 volts with a ±0.2% maximum error. The reference voltage is also available for external applications.The AD669 is both dc and ac specified. DC specs include ±1 LSB INL error and ±1 LSB DNL error. AC specs include 0.009% THD+ N and 83 dB SNR. The ac specifications make the AD669 suitable for signal generation applications.The double-buffered latches on the AD669 eliminate data skew errors while allowing simultaneous updating of DACs in multi-DAC systems.The output range is a pin-programmable unipolar 0 V to +10 V or bipolar –10 V to +10 V output. No external components are necessary to set the desired output range.The AD669 is available in versions compliant with MIL-STD-883. Refer to the Analog Devices Military Products Databook or current AD669/883B data sheet for detailed specifications. |
AD67616-Bit Parallel 100 kSPS Sampling ADC | Development Boards, Kits, Programmers | 7 | Active | The AD676 is a multipurpose 16-bit parallel output analog-to-digital converter which utilizes a switched-capacitor/charge redistribution architecture to achieve a 100 kSPS conversion rate (10 µs total conversion time). Overall performance is optimized by digitally correcting internal nonlinearities through on-chip autocalibration.The AD676 circuitry is segmented onto two monolithic chips- a digital control chip fabricated on Analog Devices DSP CMOS process and an analog ADC chip fabricated on our BiMOS II process. Both chips are contained in a single package.The AD676 is specified for ac (or "dynamic") parameters such as S/(N+D) Ratio, THD and IMD which are important in signal processing applications. In addition, dc parameters are specified which are important in measurement applications.The AD676 operates from +5 V and ±12 V supplies and typically consumes 360 mW during conversion. The digital supply (VDD) is separated from the analog supplies (VCC, VEE) for reduced digital crosstalk. An analog ground sense is provided for the analog input. Separate analog and digital grounds are also provided.The AD676 is available in a 28-pin plastic DIP or 28-pin side-brazed ceramic package. A serial-output version, the AD677, is available in a 16-pin 300 mil wide ceramic or plastic package. |
AD67716-Bit, Serial, 100 kSPS Sampling ADC. | Evaluation Boards | 7 | Active | The AD677 is a multipurpose 16-bit serial output analog-to- digital converter which utilizes a switched-capacitor/charge redistribution architecture to achieve a 100 kSPS conversion rate (10 µs total conversion time). Overall performance is optimized by digitally correcting internal nonlinearities through on-chip autocalibration.The AD677 circuitry is segmented onto two monolithic chips- a digital control chip fabricated on Analog Devices DSP CMOS process and an analog ADC chip fabricated on our BiMOS II process. Both chips are contained in a single package.The AD677 is specified for ac (or "dynamic") parameters such as S/(N+D) Ratio, THD and IMD which are important in signal processing applications. In addition, dc parameters are specified which are important in measurement applications.The AD677 operates from +5 V and ±12 V supplies and typically consumes 450 mW using a 10 V reference (360 mW with 5 V reference) during conversion. The digital supply (VDD) is separated from the analog supplies (VCC, VEE) for reduced digital crosstalk. An analog ground sense is provided to remotely sense the ground potential of the signal source. This can be useful if the signal has to be carried some distance to the A/D converter. Separate analog and digital grounds are also provided.The AD677 is available in a 16-pin narrow plastic DIP, 16-pin narrow side-brazed ceramic package, or 28-lead SOIC. A parallel output version, the AD676, is available in a 28-pin ceramic or plastic DIP. All models operate over a commercial temperature range of 0°C to +70°C or an industrial range of -40°C to +85°C.PRODUCT HIGHLIGHTSAutocalibration provides excellent dc performance while eliminating the need for user adjustments or additional external circuitry.±5 V to ±10 V input range (±VREF).Available in 16-pin 0.3" skinny DIP or 28-lead SOIC.Easy serial interface to standard ADI DSPs.TTL compatible inputs/outputs.Excellent ac performance: –99 dB THD, 92 dB S/(N+D) peak spurious –101 dB.Industry leading dc performance: 1.0 LSB INL, ±1 LSB full scale and offset. |
AD67812-Bit 200 kSPS Complete Sampling ADC | Integrated Circuits (ICs) | 6 | Active | The AD678 is a complete, multipurpose 12-bit monolithic analog-to-digital converter, consisting of a sample-hold amplifier (SHA), a microprocessor compatible bus interface, a voltage reference and clock generation circuitry.The AD678 is specified for ac (or "dynamic") parameters such as S/N+D ratio, THD and IMD which are important in signal processing applications. In addition, the AD678K, B and T grades are fully specified for dc parameters which are important in measurement applications.The AD678 offers a choice of digital interface formats; the 12 data bits can be accessed by a 16-bit bus in a single read operation or by an 8-bit bus in two read operations (8+4), with right or left justification. Data format is straight binary for unipolar mode and twos complement binary for bipolar mode. The input has a full-scale range of 10 V with a full power bandwidth of 1 MHz and a full linear bandwidth of 500 kHz. High input impedance (10 MΩ) allows direct connection to unbuffered sources without signal degradation.This product is fabricated on Analog Devices' BiMOS process, combining low power CMOS logic with high precision, low noise bipolar circuits; laser-trimmed thin-film resistors provide high accuracy. The converter utilizes a recursive subranging algorithm which includes error correction and flash converter circuitry to achieve high speed and resolution.The AD678 operates from +5 V and ±12 V supplies and dissipates 560 mW (typ). The AD678 is available in 28-pin plastic DIP, ceramic DIP, and 44 J-leaded ceramic surface mount packages.Screening to MIL-STD-883C Class B is also available.PRODUCT HIGHLIGHTSCOMPLETE INTEGRATION: The AD678 minimizes external component requirements by combining a high speed sample-hold amplifier (SHA), ADC, 5 V reference, clock and digital interface on a single chip. This provides a fully specified sampling A/D function unattainable with discrete designs.SPECIFICATIONS: The AD678K, B and T grades provide fully specified and tested ac and dc parameters. The AD678J, A and S grades are specified and tested for ac parameters; dc accuracy specifications are shown as typicals. DC specifications (such as INL, gain and offset) are important in control and measurement applications. AC specifications (such as S/N+D ratio, THD and IMD) are of value in signal processing applications.EASE OF USE: The pinout is designed for easy board lay-out, and the choice of single or two read cycle output provides compatibility with 16- or 8-bit buses. Factory trimming eliminates the need for calibration modes or external trimming to achieve rated performance.RELIABILITY: The AD678 utilizes Analog Devices’ monolithic BiMOS technology. This ensures long-term reliability compared to multichip and hybrid designs.UPGRADE PATH: The AD678 provides the same pinout as the 14-bit, 128 kSPS AD679 ADC.The AD678 is available in versions compliant with MIL-STD-883. Refer to the Analog Devices Military Products Databook or current AD678/883B data sheet for detailed specifications. |
| Integrated Circuits (ICs) | 8 | Active | |
