Analog Devices

The AD6636 is a (Digital) Receive Signal Processor intended for direct IF sampling or highly sampled baseband radios requiring wide-bandwidth input signals. It has been optimized for the demanding filtering requirements of wideband standards like, CDMA2000, UMTS, and TD-SCDMA. The AD6636 is designed to be used as part of radio system that uses either an IF sampling ADC, or a baseband sampling ADC.The AD6636 has the following signal processing stages: a Frequency Translator, a 5th order Cascaded Integrated Comb filter, two sets of Cascaded Fixed Coefficient Finite Impulse Response (FIR) and Half Band filters, three cascaded programmable coefficient Sum of Product FIR filters, an Interpolating Half Band Filter (LHB) and a digital Automatic Gain Control (AGC) Block. Multiple modes are supported for clocking data into and out of the chip to provide flexibility for interfacing to a wide variety of digitizers. Programming and control is accomplished via serial or microport interfaces.The AD6636 features a fractional clock multiplier that uses the ADC clock to produce a digital down converter master clock up to 200 MHz. This internal phased-locked loop (PLL) allows optimum digital clock rates, regardless of the converter sampling rate, enabling the best possible digital signal decimation and filtering. Three 16-bit parallel output ports accommodate high data rate 3G applications. An on-chip interpolating half band filter can also be used to further increase the output rate while still allowing for very efficient filters. In addition, each channel has a digital AGC for output data scaling.

The AD6640 is a high speed, high performance, low power, monolithic 12-bit analog-to-digital converter. All necessary functions, including track-and-hold (T/H) and reference, are included on-chip to provide a complete conversion solution. The AD6640 runs on a single 5 V supply and provides CMOS compatible digital outputs at 65 MSPS.Specifically designed to address the needs of multichannel, multimode receivers, the AD6640 maintains 80 dB spurious-free dynamic range (SFDR) over a bandwidth of 25 MHz. Noise performance is also exceptional: typical signal-to-noise ratio is 68 dB.The AD6640 is built on Analog Devices’ high speed complementary bipolar process (XFCB) and uses an innovative multipass architecture. Units are packaged in a 44-lead plastic quad flatpack (LQFP) specified from –40°C to +85°C.APPLICATIONSCellular/PCS Base StationsMultichannel, Multimode ReceiversGPS Anti-Jamming ReceiversCommunications ReceiversPhased Array Receivers

The AD6641 is a 250 MHz bandwidth digital predistortion (DPD) observation receiver that integrates a 12-bit 500 MSPS ADC, a 16k × 12 FIFO, and a multimode back end that allows users to retrieve the data through a serial port (SPORT), the SPI interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVDS port after being stored in the integrated FIFO memory. It is optimized for outstanding dynamic performance and low power consumption and is suitable for use in telecommunications applications such as a digital predistortion observation path where wider bandwidths are desired. All necessary functions, including the sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution.The on-chip FIFO allows small snapshots of time to be captured via the ADC and read back at a lower rate. This reduces the constraints of signal processing by transferring the captured data at an arbitrary time and at a much lower sample rate. The FIFO can be operated in several user-programmable modes. In the single capture mode, the ADC data is captured when signaled via the SPI port or the use of the external FILL± pins. In the continuous capture mode, the data is loaded continuously into the FIFO and the FILL± pins are used to stop this operation.The data stored in the FIFO can be read back based on several user-selectable output modes. The DUMP pin can be asserted to output the FIFO data. The data stored in the FIFO can be accessed via a SPORT, SPI, 12-bit parallel CMOS port, or 6-bit DDR LVDS interface. The maximum output throughput supported by the AD6641 is in the 12-bit CMOS or 6-bit DDR LVDS mode and is internally limited to 1/8th of the maximum input sample rate. This corresponds to the maximum output data rate of 62.5 MHz at an input clock rate of 500 MSPS.The ADC requires a 1.9 V analog voltage supply and a differential clock for full performance operation. Output format options include twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced SiGe BiCMOS process, the device is available in a 56-lead LFCSP and is specified over the industrial temperature range (−40°C to +85°C). This product is protected by a U.S. patent.ApplicationsWireless and wired broadband communicationsCommunications test equipmentPower amplifier linearizationProduct HighlightsHigh Performance ADC Core.Maintains 65.8 dBFS SNR at 500 MSPS with a 250 MHz input.Low Power. Consumes only 695 mW at 500 MSPS.Ease of Use.On-chip 16k FIFO allows the user to target the high performance ADC to the time period of interest and reduce the constraints of processing the data by transferring it at an arbitrary time and a lower sample rate. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.9 V supply simplifies system power supply design.Serial Port Control.Standard serial port interface supports configuration of the device and customization for the user’s needs.1.9 V or 3.3 V SPI and Serial Data Port Operation.

The AD6643 is an 11-bit, 200 MSPS/250 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic, and each ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the SPI. With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6643 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution.The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 185 MSPS, the AD6643 can achieve up to 75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode.When the NSR block is disabled, the ADC data is provided directly to the output at a resolution of 11 bits. The AD6643 can achieve up to 66.5 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6643 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are required.After digital signal processing, multiplexed output data is routed into an 11-bit output port such that the maximum data rate is 400 Mbps (DDR). These outputs are LVDS and support ANSI-644 levels.The AD6643 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of a separate antenna. This IF sampling architecture greatly reduces compo-nent cost and complexity compared with traditional analog techniques or less integrated digital methods.Flexible power-down options allow significant power savings. Programming for device setup and control is accomplished using a 3-wire SPI-compatible serial interface with numerous modes to support board level system testing.The AD6643 is available in a Pb-free, RoHS-compliant, 64-lead, 9 mm × 9 mm lead frame chip scale package (LFCSP_VQ) and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.Product HighlightsTwo ADCs are contained in a small, space-saving, 9 mm × 9 mm × 0.85 mm, 64-lead LFCSP package.Pin selectable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of up to 60 MHz at 185 MSPS.LVDS digital output interface configured for low cost FPGA families.Operation from a single 1.8 V supply.Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode.On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems.ApplicationsCommunicationsDiversity radio and smart antenna (MIMO) systemsMultimode digital receivers (3G)WCDMA, LTE, CDMA2000WiMAX, TD-SCDMAI/Q demodulation systemsGeneral-purpose software radios

The AD6645 is a high speed, high performance, monolithic 14-bit analog-to-digital converter (ADC). All necessary functions, including track-and-hold (T/H) and reference, are included on the chip to provide a complete conversion solution. The AD6645 provides CMOS-compatible digital outputs. It is the fourth generation in a wideband ADC family, preceded by theAD9042(12-bit, 41 MSPS), theAD6640(12-bit, 65 MSPS, IF sampling), and theAD6644(14-bit, 40 MSPS/65 MSPS).Designed for multichannel, multimode receivers, the AD6645 is part of the Analog Devices, Inc., SoftCell®transceiver chipset. The AD6645 maintains 100 dB multitone, spurious-free dynamic range (SFDR) through the second Nyquist band. This breakthrough performance eases the burden placed on multimode digital receivers (software radios) that are typically limited by the ADC. Noise performance is exceptional; typical signal-to-noise ratio (SNR) is 74.5 dB through the first Nyquist band.The AD6645 is built on the Analog Devices extra fast complementary bipolar (XFCB) process and uses an innovative, multipass circuit architecture. Units are available in a 52-lead exposed pad (TQFP_EP) package specified from −40°C to +85°C at 80 MSPS and −10°C to +85°C at 105 MSPS.Product HighlightsIF Sampling. The AD6645 maintains outstanding ac performance up to input frequencies of 200 MHz, suitable for multicarrier 3G wideband cellular IF sampling receivers.Pin Compatibility. The ADC has the same footprint and pin layout as the AD6644 14-bit, 40 MSPS/65 MSPS ADC.SFDR Performance and Oversampling. Multitone SFDR performance of 100 dBFS can reduce the requirements of high end RF components.ApplicationsMultichannel, multimode receiversBase station infrastructuresAMPS, IS-136, CDMA, GSM, W-CDMASingle channel digital receiversAntenna array processingCommunications instrumentationRadars, infrared imagingInstrumentation

The AD6654 is a mixed-signal IF to base band receiver consisting of a 14-bit, 92.16 MSPS analog-to-digital converter (ADC) and a four/six channel, multi-mode digital down converter (DDC) capable of processing up to six WCDMA (Wideband Code Division Multiple Access) channels. It has been optimized for the demanding filtering requirements of wideband standards such as CDMA2000, UMTS, and TD-SCDMA. The AD6654 is used as part of a radio system that digitally demodulates and filters IF sampled signals.PRODUCT HIGHLIGHTSIntegrated 14-bit, 92.16 MSPS ADCT/H (track-and-hold amplifier) analog input for excellent IF sampling up to 200MHzSix Independent Digital Filtering ChannelsRMS/Peak power monitoring of the ADC data port and 96dB range AGCs before the output portsThree programmable RAM coefficient filters, three half-band filters, two fixed coefficient filters, and one 5th order CIC filter per channelComplex filtering by combining filtering capability of multiple channelsThree 16-bit Parallel output ports operating at up to 200MHz clockBlackfin®and TigerSHARC®compatible 8/16-bit Microprocessor portSynchronous Serial communications port is compatible with most serial interface standards, SPORT, SPI, SSR etc.APPLICATIONSMulticarrier, multimode digital receiversGSM, EDGE, PHS, UMTS, WCDMA, CDMA2000, TD-SCDMA, WiMAXMicro and pico cell systems, software radiosWireless local loopSmart antenna systemsIn-building wireless telephonyBroadband data applicationsInstrumentation and test equipment

The AD6655 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS ADCs and a wideband digital downconverter (DDC). The AD6655 is designed to support communications applications where low cost, small size, and versatility are desired.The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.ADC data outputs are internally connected directly to the digital downconverter (DDC) of the receiver, simplifying layout and reducing interconnection parasitics. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO)), a half-band decimating filter, a fixed FIR filter, and an fADC/8 fixed-frequency NCO.In addition to the receiver DDC, the AD6655 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with short latency.In addition, the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect bits of the ADC with low latency. If the input signal level exceeds the programmable threshold, the coarse upper threshold indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition.The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.After digital processing, data can be routed directly to the two external 14-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or as 1.8 V LVDS. The CMOS data can also be output in an interleaved configuration at a double data rate using only Port A.The AD6655 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface.The AD6655 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.Product HighlightsIntegrated dual, 14-bit, 150 MSPS ADC.Integrated wideband decimation filter and 32-bit complex NCO.Fast overrange detect and signal monitor with serial output.Proprietary differential input maintains excellent SNR performance for input frequencies up to 450 MHz.Flexible output modes, including independent CMOS, interleaved CMOS, IQ mode CMOS, and interleaved LVDS.SYNC input allows synchronization of multiple devices.3-bit SPI port for register programming and register readback.ApplicationsCommunicationsDiversity radio systemsMultimode digital receivers (3G)TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTEI/Q demodulation systemsSmart antenna systemsGeneral-purpose software radiosBroadband data applications

The AD667 is a complete voltage output 12-bit digital-to-analog converter including a high stability buried Zener voltage reference and double-buffered input latch on a single chip. The converter uses 12 precision high speed bipolar current steering switches and a laser trimmed thin-film resistor network to provide fast settling time and high accuracy.Microprocessor compatibility is achieved by the on-chip double-buffered latch. The design of the input latch allows direct interface to 4-, 8-, 12-, or 16-bit buses. The 12 bits of data from the first rank of latches can then be transferred to the second rank, avoiding generation of spurious analog output values. The latch responds to strobe pulses as short as 100 ns, allowing use with the fastest available microprocessors.The functional completeness and high performance in the AD667 results from a combination of advanced switch design, high speed bipolar manufacturing process, and the proven laser wafer-trimming (LWT) technology. The AD667 is trimmed at the wafer level and is specified to ±1/4 LSB maximum linearity error (K, B grades) at +25°C and ±1/2 LSB over the full operating temperature range.The subsurface (buried) Zener diode on the chip provides a low noise voltage reference which has long-term stability and temperature drift characteristics comparable to the best discrete reference diodes. The laser trimming process which provides the excellent linearity, is also used to trim the absolute value of the reference as well as its temperature coefficient. The AD667 is thus well suited for wide temperature range performance with ±1/2 LSB maximum linearity error and guaranteed monotonicity over the full temperature range. Typical full-scale gain TC is 5 ppm/°C.The AD667 is available in five performance grades. The AD667J and K are specified for use over the 0°C to +70°C temperature range and are available in a 28-pin molded plastic DIP (N) or PLCC (P) package. The AD667S grade is specified for the -55°C to +125°C range and is available in the ceramic DIP (D) or LCC (E) package. The AD667A and B are specified for use over the -25°C to +85°C temperature range and are available in a 28-pin hermetically sealed ceramic DIP (D) package.