Analog Devices

The AD637 is a complete, high accuracy, rms-to-dc converter that computes the true rms value of any complex waveform. It offers performance that is unprecedented in integrated circuit rms-to-dc converters and comparable to discrete and modular techniques in accuracy, bandwidth, and dynamic range. The AD637 computes the true root mean square, mean square, or absolute value of any complex ac (or ac plus dc) input waveform and gives an equivalent dc output voltage. The true rms value of a waveform is more useful than an average rectified signal because it relates directly to the power of the signal. The rms value of a statistical signal relates to the standard deviation of the signal.Superior crest factor compensation permits measurements of signals with crest factors of up to 10 with less than 1% additional error. The wide bandwidth of the AD637 permits the measurement of signals up to 600 kHz with inputs of 200 mV rms and up to 8 MHz when the input levels are above 1 V rms.Direct dB value of the rms output with a range of 60 dB is available on a separate pin. An externally programmed reference current allows the user to select the 0 dB reference voltage to correspond to any level between 0.1 V and 2.0 V rms.A chip select connection on the AD637 permits the user to decrease the supply current from 2.2 mA to 350 µA during periods when the rms function is not in use. This feature facilitates the addition of precision rms measurement to remote or handheld applications where minimum power consumption is critical. In addition, when the AD637 is powered down, the output goes to a high impedance state. This allows several AD637s to be tied together to form a wideband true rms multiplexer.The input circuitry of the AD637 is protected from overload voltages in excess of the supply levels. The inputs are not damaged by input signals if the supply voltages are lost.The AD637 is laser wafer trimmed to achieve rated performance without external trimming. The only external component required is a capacitor that sets the averaging period. The value of this capacitor also determines low frequency accuracy, ripple level, and settling time.The on-chip buffer amplifier is used either as an input buffer or in an active filter configuration. The filter can be used to reduce the amount of ac ripple, thereby increasing accuracy.The AD637 is available in accuracy Grade J and Grade K for commercial temperature range (0°C to 70°C) applications, accuracy Grade A and Grade B for industrial range (−40°C to +85°C) applications, and accuracy Grade S rated over the −55°C to +125°C temperature range. All versions are available in hermetically sealed, 14-lead SBDIP, 14-lead CERDIP, and 16-lead SOIC_W packages.

The AD640 is a complete monolithic logarithmic amplifier. A single AD640 provides up to 50 dB of dynamic range for frequencies from dc to 120 MHz. Two AD640s in cascade can provide up to 95 dB of dynamic range at reduced bandwidth. The AD640 uses a successive detection scheme to provide an output current proportional to the logarithm of the input voltage. It is laser calibrated to close tolerances and maintains high accuracy over the full military temperature range using supply voltages from ±4.5 V to ±7.5 V.The AD640 comprises five cascaded dc-coupled amplifier/limiter stages, each having a small signal voltage gain of 10 dB and a –3 dB bandwidth of 350 MHz. Each stage has an associated full-wave detector, whose output current depends on the absolute value of its input voltage. The five outputs are summed to provide the video output (when low-pass filtered) scaled at 1 mA per decade (50 µA per dB). On chip resistors can be used to convert this output current to a voltage with several convenient slope options. A balanced signal output at +50 dB (referred to input) is provided to operate AD640s in cascade.The logarithmic response is absolutely calibrated to within ±1 dB for dc or square wave inputs from ±0.75 mV to ±200 mV, with an intercept (logarithmic offset) at 1 mV dc. An integral X10 attenuator provides an alternative input range of ±7.5 mV to ±2 V dc. Scaling is also guaranteed for sinusoidal inputs.The AD640B is specified for the industrial temperature range of –40°C to +85°C and the AD640T, available processed to MILSTD-883B, for the military range of –55°C to +125°C. Both are available in 20-lead side-brazed ceramic DIPs or leadless chip carriers (LCC). The AD640J is specified for the commercial temperature range of 0°C to +70°C, and is available in both 20-lead plastic DIP (N) and PLCC (P) packages. This device is now available to Standard Military Drawing (DESC) number 5962-9095501MRA and 5962-9095501M2A.Product HighlightsAbsolute calibration of a wideband logarithmic amplifier is unique. The AD640 is a high accuracy measurement device, not simply a logarithmic building block.Advanced design results in unprecedented stability over the full military temperature range.The fully differential signal path greatly reduces the risk of instability due to inadequate power supply decoupling and shared ground connections, a serious problem with commonly used unbalanced designs.Differential interfaces also ensure that the appropriate ground connection can be chosen for each signal port. They further increase versatility and simplify applications. The signal input impedance is ~500 kΩ in shunt with ~2 pF.The dc-coupled signal path eliminates the need for numerous interstage coupling capacitors and simplifies logarithmic conversion of subsonic signals.The low input offset voltage of 50 µV (200 µV max) ensures good accuracy for low level dc inputs.Thermal recovery "tails," which can obscure the response when a small signal immediately follows a high level input, have been minimized by special attention to design details.The noise spectral density of 2 nV/√Hzresults in a noise floor of ~23 µV rms (–80 dBm) at a bandwidth of 100 MHz. The dynamic range using cascaded AD640s can be extended to 95 dB by the inclusion of a simple filter between the two devices.ApplicationsRadar, sonar, ultrasonic and audio systemsPrecision instrumentation from DC to 120 MHzPower measurement with absolute calibrationWide range high accuracy signal compressionAlternative to discrete and hybrid IF stripsReplaces several discrete log amp ICs

The AD648 is a matched pair of low power, precision monolithic operational amplifiers. It offers both low bias current (10 pA max, warmed up) and low quiescent current (400 µA max) and is fabricated with ion-implanted FET and laser wafer trimming technologies. Input bias current is guaranteed over the AD648's entire common-mode voltage range.The economical J grade has a maximum guaranteed offset voltage of less than 2 mV and an offset voltage drift of less than 20 µV/°C. The combination of low quiescent current and low offset voltage drift minimizes changes in input offset voltage due to self-heating effects.The AD648 is recommended for any dual supply op amp application requiring low power and excellent dc and ac performance. In applications such as battery-powered, precision instrument front ends and CMOS DAC buffers, the AD648's excellent combination of low input offset voltage and drift, low bias current and low 1/f noise reduces output errors. High common-mode rejection and high open-loop gain ensures better than 12-bit linearity in high impedance, buffer applications.The AD648 is pinned out in a standard dual op amp configuration and is available in seven performance grades. The AD648J and AD648K are rated over the commercial temperature range of 0°C to +70°C.The AD648 is available in an 8-pin plastic mini-DIP and SOIC package.

The AD650 V/F/V (voltage-to-frequency or frequency-to-voltage converter) provides a combination of high frequency operation and low nonlinearity previously unavailable in monolithic form. The inherent monotonicity of the V/F transfer function makes the AD650 useful as a high-resolution analog-to-digital converter. A flexible input configuration allows a wide variety of input voltage and current formats to be used, and an open-collector output with separate digital ground allows simple interfacing to either standard logic families or opto-couplers.The linearity error of the AD650 is typically 20 ppm (0.002% of full scale) and 50 ppm (0.005%) maximum at 10 kHz full scale. This corresponds to approximately 14-bit linearity in an analog-to-digital converter circuit. Higher full-scale frequencies or longer count intervals can be used for higher resolution conversions. The AD650 has a useful dynamic range of six decades allowing extremely high resolution measurements. Even at 1 MHz full scale, linearity is guaranteed less than 1000 ppm (0.1%) on the AD650KN, KP, BD and SD grades.In addition to analog-to-digital conversion, the AD650 can be used in isolated analog signal transmission applications, phased locked-loop circuits, and precision stepper motor speed controllers. In the F/V mode, the AD650 can be used in precision tachometer and FM demodulator circuits.The input signal range and full-scale output frequency are user-programmable with two external capacitors and one resistor. Input offset voltage can be trimmed to zero with an external potentiometer.The AD650JN and AD650KN are offered in a plastic 14-pin DIP package. The AD650JP and AD650KP are available in a 20-pin plastic leaded chip carrier (PLCC). Both plastic packaged versions of the AD650 are specified for the commercial (0°C to +70°C) temperature range. For industrial temperature range (-25°C to +85°C) applications, the AD650AD and AD650BD are offered in a ceramic package. The AD650SD is specified for the full -55°C to +125°C extended temperature range.

The AD660 DACPORT®is a complete 16-bit monolithic digital-to-analog converter with an on-board voltage reference, double-buffered latches, and an output amplifier. It is manufactured on the Analog Devices, Inc., BiMOS II process. This process allows the fabrication of low power CMOS logic functions on the same chip as high precision bipolar linear circuitry.The AD660 architecture ensures 15-bit monotonicity over time and temperature. Integral and differential nonlinearity is maintained at ±0.003% maximum. The on-chip output amplifier provides a voltage output settling time of 10 μs to within ½ LSB for a full-scale step.The AD660 has an extremely flexible digital interface. Data can be loaded into the AD660 in serial mode or as two 8-bit bytes. This is made possible by two digital input pins that have dual functions. The serial mode input format is pin selectable to be MSB or LSB first. The serial output pin allows the user to daisy-chain several AD660 devices by shifting the data through the input latch into the next DAC, thus minimizing the number of control lines required to SIN,CSand LDAC. The byte mode input format is also flexible in that the high byte or low byte data can be loaded first. The double buffered latch structure eliminates data skew errors and provides for simultaneous updating of DACs in a multiDAC system.The AD660 is available in five grades. AN and BN versions are specified from −40°C to +85°C and are packaged in a 24-lead300 mil plastic DIP. AR and BR versions are also specified from −40°C to +85°C and are packaged in a 24-lead SOIC. The SQ version is packaged in a 24-lead 300 mil CERDIP package and is also available compliant to MIL-STD-883. Refer to the AD660SQ/883B military data sheet for specifications and test conditions.PRODUCT HIGHLIGHTSThe AD660 is a complete 16-bit DAC, with a voltage reference, double-buffered latches, and an output amplifier on a single chip.The internal buried Zener reference is laser trimmed to 10.000 V with a ±0.1% maximum error and a temperature drift performance of ±15 ppm/°C. The reference is available for external applications.The output range of the AD660 is pin programmable and can be set to provide a unipolar output range of 0 V to 10 V or a bipolar output range of −10 V to +10 V. No external components are required.The AD660 is both dc and ac specified. DC specifications include ±1 LSB INL and ±1 LSB DNL errors. AC specifications include 0.009% THD + N and 83 dB SNR.The double-buffered latches on the AD660 eliminate data skew errors and allow simultaneous updating of DACs in multiDAC applications.The clear function can asynchronously set the output to 0 V regardless of whether the DAC is in unipolar or bipolar mode.The output amplifier settles within 10 μs to ±½ LSB for a full-scale step and within 2.5 μs for a 1 LSB step over temperature. The output glitch is typically 15 nV-s when a full-scale step is loaded.Data Sheet, Rev. B, 6/08

Analog Devices' innovative Diversity Receiver chipset delivers two IF-to-baseband diversity channels in a compact, comprehensive solution that incorporates Automatic Gain Control, Received Signal Strength Indicator, high-resolution. Numerically Controlled Oscillator and digital filtering on-chip.The chipset comprises Analog Devices' AD6600 dual-channel IF sampling analog-to-digital converter and AD6620 dual-channel decimating receiver chip. Configured with the appropriate external components, it can address a variety of air interface standards, including GSM, CDMA, IS136 and PHS, as well as proprietary modulation schemes for paging systems and wireless fixed access receivers.Based on Analog Devices' next-generation receiver architecture, the Diversity Receiver replaces sensitive analog filters with digital filters for significant cost and size reductions. Complete reference designs show the optimal layout for reducing noise and minimizing cross-channel coupling.

The AD6623 is a four channel Transmit Signal Processor (TSP) that creates high bandwidth data for Transmit Digital-to-Analog Converters (TxDAC®s) from baseband data provided by a Digital Signal Processor (DSP). Modern TxDACs have achieved sufficiently high sampling rates, analog bandwidth, and dynamic range to create the first Intermediate Frequency (IF) directly. The AD6623 synthesizes multi-carrier and multi-standard digital signals to drive these TxDACs. The RAM-based architecture allows easy reconfiguration for multi-mode applications. Modulation, pulse-shaping and anti-imaging filters, static equalization, and tuning functions are combined in a single, cost-effective device. Digital IF signal processing provides repeatable manufacturing, higher accuracy, and more flexibility than comparable high dynamic range analog designs.The AD6623 is pin compatible to the AD6622 and can operate in AD6622 compatible control register mode.Each TSP has five cascaded signal processing elements: a programmable interpolating RAM Coefficient Filter (RCF), a programmable Scale and Power Ramp, a programmable 5th order Cascaded Integrator Comb (CIC5) interpolating filter, a flexible 2nd order Re-Sampling Cascaded Integrator Comb filter (rCIC2), and a Numerically Controlled Oscillator/tuner (NCO). The AD6623 has four identical digital TSPs complete with synchronization circuitry and cascadable wideband channel summation. The outputs of the four TSPs are summed and scaled on-chip. In multi-carrier channel wideband transmitters, a bi-directional bus allows the Parallel (wideband) IF Input/Output to drive a second DAC. In this operational mode two AD6623 channels drive one DAC and the other two AD6623 channels drive a second DAC. Multiple AD6623s may be combined by driving the INOUT[17:0] of the succeeding with the OUT[17:0] of the preceding chip. The INOUT[17:0] can alternatively be masked off by software to allow preceding AD6623s outputs to be ignored.Each channel accepts input data from independent serial ports that may be connected directly to the serial port of Digital Signal Processor (DSP) chips. The AD6623 utilizes a 3.3V I/O power supply and a 2.5V core power supply. All I/O pins are 5V tolerant. All control registers and coefficient values are programmed through a generic microprocessor interface. Intel and Motorola microprocessor bus modes are supported. All inputs and outputs are LVCMOS compatible.ApplicationsCellular/PCS Base StationsMicro/Pico Cell Base StationsWireless Local Loop Base StationsMulticarrier, Multimode Digital TransmitGSM, EDGE, IS136, PHS, IS95, TDS CDMA, UMTS, CDMA2000Phased Array Beam Forming AntennasSoftware Defined RadioTuning Resolution Better than 0.025 HzReal or Complex Outputs

The AD6633 is a multi-channel, wide-bandwidth (Digital) Transmit Signal Processor (TSP) with VersaCREST™crest reduction engine. It processes digital baseband input data and generates wideband, real or complex output data. It drives Intermediate Frequency (IF) sampling Digital to Analog Converters (DACs) at sample rates up to 125 Mega Samples Per Second (MSPS). Up to six wideband modulated carriers per package can be achieved from a single output port. Devices may be connected together for additional channels by using multiple packages. Interpolation, anti-imaging filtering, all pass equalization, and NCO tuning functions are combined in a single, cost-effective device which includes the VersaCREST™crest factor reduction engine.Each VersaCREST™wideband channel contains a peak-to-average compensation block that reduces Power Amplifier (PA) requirements. By minimizing infrequent peaks in Code-Division Multiple-Access (CDMA) signals, a PA with one-half to one-quarter the previously necessary power capacity can be used. This is done within standard signal quality requirements, and significantly lowers system cost.VersaCREST is a trademark of Analog Devices Inc.APPLICATIONSCellular/PCS basestationsMicro/pico cell basestationsMulticarrier cdma2000®, WCDMA, TD-SCDMA basestationsBroadband wireless access head ends (LMDS, MMDS)Software defined radiosHigh speed signal processing applications