Analog Devices

The AD9277 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA); an anti-aliasing filter (AAF); a 14-bit, 10 MSPS to 50 MSPS analog-to-digital converter (ADC); and an I/Q demodulator with programmable phase rotation.Each channel features a variable gain range of 42 dB, a fully differ-ential signal path, an active input preamplifier termination, a maximum gain of up to 52 dB, and an ADC with a conversion rate of up to 50 MSPS. The channel is optimized for dynamic performance and low power in applications where a small package size is critical.The LNA has a single-ended-to-differential gain that is selectable through the SPI. The LNA input noise is typically 0.75 nV/√Hz at a gain of 21.3 dB, and the combined input-referred noise of the entire channel is 0.85 nV/√Hz at maximum gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the input SNR is roughly 92 dB. In CW Doppler mode, each LNA output drives an I/Q demodulator. Each demodulator has inde-pendently programmable phase rotation through the SPI with 16 phase settings.The AD9277 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO±) for capturing data on the output and a frame clock (FCO±) trigger for signaling a new output byte are provided.Powering down individual channels is supported to increase battery life for portable applications. A standby mode option allows quick power-up for power cycling. In CW Doppler opera-tion, the VGA, AAF, and ADC are powered down. The power of the TGC path scales with selectable ADC speed power modes.The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudo-random patterns, and custom user-defined test patterns entered via the serial port interface.Fabricated in an advanced CMOS process, the AD9277 is available in a 16 mm × 16 mm, RoHS compliant, 100-lead TQFP. It is specified over the industrial temperature range of −40°C to +85°C.ApplicationsMedical imaging/ultrasoundAutomotive radar

The AD9278 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA); an anti-aliasing filter (AAF); a 12-bit, 10 MSPS to 65 MSPS analog-to-digital converter (ADC); and an I/Q demodulator with programmable phase rotation.Each channel features a variable gain range of 45 dB, a fully differential signal path, an active input preamplifier termination, a maximum gain of up to 51 dB, and an ADC with a conversion rate of up to 65 MSPS. The channel is optimized for dynamic performance and low power in applications where a small package size is critical.The LNA has a single-ended-to-differential gain that is selectable through the SPI. The LNA input noise is typically 1.3 nV/√Hz at a gain of 21.3 dB, and the combined input-referred noise of the entire channel is 1.3 nV/√Hz at maximum gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the input SNR is roughly 88 dB. In CW Doppler mode, each LNA output drives an I/Q demodulator. Each demodulator has independently programmable phase rotation through the SPI with 16 phase settings.The AD9278 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO±) for capturing data on the output and a frame clock (FCO±) trigger for signaling a new output byte are provided.Powering down individual channels is supported to increase battery life for portable applications. A standby mode option allows quick power-up for power cycling. In CW Doppler operation, the VGA, AAF, and ADC are powered down. The power of the TGC path scales with selectable ADC speed power modes.The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudo-random patterns, and custom user-defined test patterns entered via the serial port interface.Fabricated in an advanced BiCMOS process, the AD9278 is available in a 10 mm × 10 mm, RoHS compliant, 144-lead BGA. It is specified over the industrial temperature range of −40°C to +85°C.

The AD9281 is a complete dual channel, 28 MSPS, 8-bit CMOS ADC. The AD9281 is optimized specifically for applications where close matching between two ADCs is required (e.g., I/Q channels in communications applications). The 28 MHz sampling rate and wide input bandwidth will cover both narrow-band and spread-spectrum channels. The AD9281 integrates two 8-bit, 28 MSPS ADCs, two input buffer amplifiers, an internal voltage reference and multiplexed digital output buffers.

The AD9286 is an 8-bit, monolithic sampling, analog-to-digital converter (ADC) that supports interleaved operation and is optimized for low cost, low power, and ease of use. Each ADC operates at up to a 250 MSPS conversion rate with outstanding dynamic performance.The AD9286 takes a single sample clock and, with an on-chip clock divider, time interleaves the two ADC cores (each running at one-half the clock frequency) to achieve the rated 500 MSPS. By using the SPI, the user can accurately adjust the timing of the sampling edge per ADC to minimize the image spur energy.The ADC requires a single 1.8 V supply and an encode clock for full performance operation. No external reference components are required for many applications. The digital outputs are LVDS compatible.The AD9286 is available in a Pb-free, 48-lead LFCSP that is specified over the industrial temperature range of −40°C to +85°C.PRODUCT HIGHLIGHTSIntegrated 8-bit, 500 MSPS ADC.Single 1.8 V supply operation with LVDS outputs.Power-down option controlled via a pin-programmable setting.APPLICATIONSBattery-powered instrumentsHandheld scope metersLow cost digital oscilloscopesOTS: video over fiber

The AD9287 is a quad, 8-bit, 100 MSPS analog-to-digital con- verter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 100 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface (SPI).The AD9287 is available in an RoHS compliant, 48-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C.Product HighlightsSmall Footprint. Four ADCs are contained in a small, space-saving package.Low power of 133 mW/channel at 100 MSPS.Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 400 MHz and supports double data rate (DDR) operation.User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements.Pin-Compatible Family. This includes the AD9219 (10-bit), AD9228 (12-bit), and AD9259 (14-bit).ApplicationsMedical imaging and nondestructive ultrasoundPortable ultrasound and digital beam-forming systemsQuadrature radio receiversDiversity radio receiversTape drivesOptical networkingTest equipment

The AD9288 is a dual 8-bit monolithic sampling analog-to-digital converter with on-chip track-and-hold circuits and is optimized for low cost, low power, small size and ease of use. The product operates at a 100 MSPS conversion rate with outstanding dynamic performance over its full operating range. Each channel can be operated independently.The ADC requires only a single 3 V (2.7 V to 3.6 V) power supply and an encode clock for full-performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS compatible and a separate output power supply pin supports interfacing with 3.3 V or 2.5 V logic.The encode input is TTL/CMOS compatible and the 8-bit digital outputs can be operated from +3 V (2.5 V to 3.6 V) supplies. User selectable options are available to offer a combination of power down modes, digital data formats and digital data timing schemes. In power-down mode, the digital outputs are driven to a high-impedance state.Fabricated on an advanced CMOS process, the AD9288 is available in a 48-pin surface mount plastic package (7x7 mm, 1.4 mm 48-Pin LQFP) specified over the industrial temperature range (-40°C to +85°C). Pin out designed for 10-bit migration.APPLICATIONSBattery-powered instrumentsHand-held scopemetersLow cost digital oscilloscopesI and Q communications