Analog Devices Inc./Maxim Integrated

The HMC678LC3C is a 2:1 Selector designed to support data transmission rates of up to 13 Gbps, and selector port operation of up to 13 GHz. The selector routes one of the two single-ended inputs to the differential output upon assertion of the proper select port. All single-ended input signals to the HMC678LC3C are terminated with 50 ohms to ground on-chip, and may be either AC or DC coupled.The outputs of the HMC678LC3C may be operated either differentially or single-ended. Outputs can be connected directly to a 50 ohm terminated system, while DC blocking capacitors may be used if the terminating system is 50 ohms to a non-ground DC voltage. The HMC678LC3C operates from a single -3.3V dc supply and is available in a ceramic RoHS compliant 3x3 mm SMT package.APPLICATIONS2:1 Multiplexer up to 13 GbpsRF ATE ApplicationsBroadband Test & MeasurementSerial Data Transmission up to 13 GbpsRedundant Path SwitchingBuilt-in Test

The HMC6787ALC5A is a compact GaAs MMIC I/Q variable gain upconverter in a leadless RoHS compliant SMT package. This device provides a small signal conversion gain of 11 dB with 17 dBc of sideband rejection, and 13 dB of gain control. The HMC6787ALC5A utilizes a RF variable gain amplifier preceded by an I/Q mixer where the LO is driven by a X2 multiplier. IF1 and IF2 mixer inputs are provided and an external 90° hybrid is needed to select the required sideband. The I/Q mixer topology reduces the need for filtering of the unwanted sideband. The HMC6787ALC5A is a much smaller alternative to hybrid style single sideband upconverter assemblies and it eliminates the need for wire bonding by allowing the use of surface mount manufacturing techniques.APPLICATIONSPoint-to-Point and Point-to-Multi-Point RadioMilitary Radar, EW & ELINTSatellite CommunicationsSensors

The HMC6789BLC5A is a compact GaAs MMIC I/Q downconverter in a 12-terminal, RoHS compliant, ceramic leadless chip carrier (LCC) package. This device provides a small signal conversion gain of 14 dB with 25 dBc of image rejection. The HMC6789BLC5A utilizes a low noise amplifier to drive the I/Q mixer where the LO is driven by a ×2 multiplier. IF1 and IF2 mixer inputs are provided and an external 90° hybrid is needed to select the required sideband. The I/Q mixer topology reduces the need for filtering of the unwanted sideband. The HMC6789BLC5A is a much smaller alternative to hybrid style single sideband downconverter assemblies and it eliminates the need for wire bonding by allowing the use of surface mount manufacturing techniques.ApplicationsPoint-to-Point and Point-to-Multi-Point RadiosMilitary Radar, EW & ELINTSatellite CommunicationsSensors

The HMC6789BLC5A is a compact GaAs MMIC I/Q downconverter in a 12-terminal, RoHS compliant, ceramic leadless chip carrier (LCC) package. This device provides a small signal conversion gain of 14 dB with 25 dBc of image rejection. The HMC6789BLC5A utilizes a low noise amplifier to drive the I/Q mixer where the LO is driven by a ×2 multiplier. IF1 and IF2 mixer inputs are provided and an external 90° hybrid is needed to select the required sideband. The I/Q mixer topology reduces the need for filtering of the unwanted sideband. The HMC6789BLC5A is a much smaller alternative to hybrid style single sideband downconverter assemblies and it eliminates the need for wire bonding by allowing the use of surface mount manufacturing techniques.ApplicationsPoint-to-Point and Point-to-Multi-Point RadiosMilitary Radar, EW & ELINTSatellite CommunicationsSensors

The HMC682LP6C(E) is a high linearity, dual channel downconverter with integrated LO amplifier in a 6×6 SMT QFN package covering 1.7 - 2.2 GHz. Excellent input IP3 performance of +25 dBm for down conversion is provided for 3G & 4G GSM/CDMA applications at an LO drive of 0 dBm. With an input 1 dB compression of +15 dBm, the RF port will accept a wide range of input signal levels. Conversion gain is 6 dB typical. The 60 - 400 MHz IF frequency response will satisfy various GSM/CDMA receive frequency plans.APPLICATIONSCellular/3G & LTE/WiMAX/4GBasestations & RepeatersGSM, CDMA & OFDMDual Density Receivers

The HMC6832 is an input selectable, 2:8 differential fanout buffer designed for low noise clock distribution. The IN_SEL control pin selects one of the two differential inputs. This input is then buffered to all eight differential outputs. The low jitter outputs of the HMC6832 lead to synchronized low noise switching of downstream circuits, such as mixers, analog-todigital converters (ADCs)/digital-to-analog converters (DACs), or serializer/deserializer (SERDES) devices. The device is capable of low voltage, positive emitter-coupled logic (LVPECL) or low voltage differential signaling (LVDS) configurations by pulling the CONFIG pin low for LVPECL or high or open (internally pulled high) for pseudo LVDS.Product HighlightsMultiple Output Configurations.The CONFIG pin allows the user to select LVPECL or LVDS output termination.Multiple Supply Voltage Operation.The HMC6832 operates at 2.5 V or 3.3 V for LVPECL terminations (2.5 V only for LVDS).Low Noise.The HMC6832 noise is low, typically from −168 dBc/Hz to −162 dBc/Hz up to 3000 MHz.Low Propagation Delay.The HMC6832 displays a low delay, less than 207 ps, typical. Channel skew is also low, ±5 ps, typical.Low Core Current.The HMC6832 has a low core current of 56 mA, typical.ApplicationsSONET, Fibre Channel, GigE clock distributionADC/DAC clock distributionLow skew and jitter clocksWireless/wired communicationsLevel translationHigh performance instrumentationMedical imagingSingle-ended to differential conversions