| Clock/Timing | 6 | Active | |
| Signal Switches, Multiplexers, Decoders | 2 | Obsolete | |
| Signal Switches, Multiplexers, Decoders | 1 | Obsolete | |
MAX9388Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers | Signal Switches, Multiplexers, Decoders | 2 | Active | The MAX9386/MAX9387/MAX9388 are fully differential, high-speed, low-jitter ECL/PECL multiplexers (muxes) with output buffer(s). The devices are designed for clock-and-data distribution applications, and feature extremely low propagation delays (318ps, typ) and output-to-output skews (3.9ps, typ). The MAX9386 is a 5:1 mux with a single output buffer. The MAX9387 is a 5:1 mux with dual output buffers, and is intended for use in redundant systems. The MAX9388 is a 4:1 mux with a single output buffer, and is pin compatible with the MC100EP57.Three single-ended select inputs, SEL0, SEL1, and SEL2, control the mux function on the MAX9386/MAX9387. The MAX9388 has two select inputs, SEL0 and SEL1. The mux select inputs are compatible with ECL/PECL logic, and are internally referenced to the on-chip output VBB, nominally VCC- 1.425V. The select inputs accept signals between VCCand VEE. Internal pulldowns to VEEensure a low-default condition if the select inputs are left open.The differential inputs D_, D_ -bar can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference output VBB. All the differential inputs have internal bias and clamping circuits that ensure low-default output states when the inputs are left open. The MAX9386/MAX9387/MAX9388 operate with a wide supply range |VCC- VEE| of 2.375V to 5.5V. The MAX9386/MAX9388 are offered in 20-pin TSSOP and QSOP packages. The MAX9387 is offered in 24-pin TSSOP and QSOP packages.ApplicationsCentral Office Backplane Clock DistributionDSLAM/DLCHigh-Speed Telecom and Datacom Applications |
MAX9389Differential 8:1 ECL/PECL Multiplexer with Dual Output Buffers | Signal Switches, Multiplexers, Decoders | 2 | Active | The MAX9389 is a fully differential, high-speed, low-jitter, 8-to-1 ECL/PECL multiplexer (mux) with dual output buffers. The device is designed for clock and data distribution applications, and features extremely low propagation delay (310ps typ) and output-to-output skew (30ps max).Three single-ended select inputs, SEL0, SEL1, and SEL2, control the mux function. The mux select inputs are compatible with ECL/PECL logic, and are internally referenced to the on-chip reference output (VBB1, VBB2), nominally VCC- 1.425V. The select inputs accept signals between VCCand VEE. Internal pulldowns to VEEensure a low default condition if the select inputs are left open.The differential inputs D_, D_ -bar can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference output (VBB1, VBB2). All the differential inputs have internal bias and clamping circuits that ensure a low output state when the inputs are left open.The MAX9389 operates with a wide 2.375V to 5.5V supply range. The device is offered in 32-pin TQFP and thin QFN packages, and operates over the -40°C to +85°C extended temperature range.ApplicationsCentral Office Backplane Clock DistributionDSLAM/DLCHigh-Speed Telecom and Datacom Applications |
| Interface | 1 | Obsolete | |
| Logic | 2 | Active | |
| Signal Switches, Multiplexers, Decoders | 1 | Active | |
| Signal Switches, Multiplexers, Decoders | 3 | Active | |
MAX9393Anything-to-LVDS Dual 2 x 2 Crosspoint Switches | Interface | 1 | Active | The MAX9392/MAX9393 dual 2 x 2 crosspoint switches perform high-speed, low-power, and low-noise signal distribution. The MAX9392/MAX9393 multiplex one of two differential input pairs to either or both low-voltage differential signaling (LVDS) outputs for each channel. Independent enable inputs turn on or turn off each differential output pair.Four LVCMOS/LVTTL logic inputs (two per channel) control the internal connections between inputs and outputs. This flexibility allows for the following configurations: 2 x 2 crosspoint switch, 2:1 mux, 1:2 splitter, or dual repeater. This makes the MAX9392/MAX9393 ideal for protection switching in fault-tolerant systems, loopback switching for diagnostics, fanout buffering for clock/data distribution, and signal regeneration.Fail-safe circuitry forces the outputs to a differential low condition for undriven inputs or when the common-mode voltage exceeds the specified range. The MAX9392 provides high-level input fail-safe detection for LVDS, HSTL, and other GND-referenced differential inputs. The MAX9393 provides low-level input fail-safe detection for LVPECL, CML, and other VCC-referenced differential inputs.Ultra-low 98ps(P-P)(max) pseudorandom bit sequence (PRBS) jitter ensures reliable communications in high-speed links that are highly sensitive to timing error, especially those incorporating clock-and-data recovery, or serializers and deserializers. The high-speed switching performance guarantees 1.5GHz operation and less than 67ps (max) skew between channels.LVDS inputs and outputs are compatible with the TIA/EIA-644 LVDS standard. The LVDS outputs drive 100Ω loads. The MAX9392/MAX9393 are offered in a 32-pin TQFP package and operate over the extended temperature range (-40°C to +85°C).Also see the MAX9390/MAX9391 for the crossflow version.ApplicationsCentral Office Backplane Clock DistributionDSLAMFault-Tolerant SystemsHigh-Speed Telecom/Datacom EquipmentProtection Switching |
