SN74HC165-EP Series
High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register
Manufacturer: Texas Instruments
Catalog
High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register
Key Features
• Controlled BaselineOne Assembly/Test Site, One Fabrication SiteExtended Temperature Performance of Up To –55°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product-Change NotificationQualification Pedigree2-V to 6-V VCCOperationOutputs Can Drive Up To 10 LSTTL LoadsLow Power Consumption, 80-µA Max ICCTypical tpd= 13 ns±4-mA Output Drive at 5 VLow Input Current of 1 µA MaxComplementary OutputsDirect Overriding Load (Data) InputsGated Clock InputsParallel-to-Serial Data ConversionComponent qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.Controlled BaselineOne Assembly/Test Site, One Fabrication SiteExtended Temperature Performance of Up To –55°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product-Change NotificationQualification Pedigree2-V to 6-V VCCOperationOutputs Can Drive Up To 10 LSTTL LoadsLow Power Consumption, 80-µA Max ICCTypical tpd= 13 ns±4-mA Output Drive at 5 VLow Input Current of 1 µA MaxComplementary OutputsDirect Overriding Load (Data) InputsGated Clock InputsParallel-to-Serial Data ConversionComponent qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
Description
AI
The SNx4HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A–H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SNx4HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Because a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LDis held high. While SH/LDis low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
The SNx4HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A–H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SNx4HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Because a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LDis held high. While SH/LDis low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
