LMK61E0-050M Series

155.52-MHz, LVPECL ±25 ppm, ultra-low jitter, standard differential oscillator

Catalog

155.52-MHz, LVPECL ±25 ppm, ultra-low jitter, standard differential oscillator

Part	Type	Supplied Contents	Primary Attributes	Secondary Attributes	Utilized IC / Part	Operating Temperature [Max]	Operating Temperature [Min]	Frequency	Function	Base Resonator	Package / Case	Frequency Stability	Current - Supply (Disable) (Max) [Max]	Output	Mounting Type	Voltage - Supply	Height - Seated (Max) [Max] [z]	Height - Seated (Max) [Max] [z]	Size / Dimension [x]	Size / Dimension [y]	Size / Dimension [x]	Size / Dimension [y]	Current - Supply (Max) [Max]	Available Frequency Range [Max]	Available Frequency Range [Min]	Programmable Type	Frequency Stability (Total)	Embedded
Texas Instruments LMK61A2-100M00EVM	Timing	Board(s)	USB Powered or External Supply	SMA Connectors	LMK61A2-100M00
Texas Instruments LMK61PDEVM	Timing	Board(s) Cable(s)	USB Powered or External Supply	On-Board LEDs	LMK61PD0A2
Texas Instruments LMK61I2-100M00EVM	Timing	Board(s)	USB Powered or External Supply	SMA Connectors	LMK61I2-100M00
Texas Instruments LMK61E0-050M00SIAR	XO (Standard)					85 °C	-40 °C	50 MHz	Enable/Disable	Silicon	6-SMD Module	25 ppm	136 mA	LVPECL	Surface Mount	3.3 V	1.15 mm	0.045 in	7 mm	5 mm	0.276 "	0.197 "	208 mA
Texas Instruments LMK61E0M-SIAT	XO (Standard)					85 °C	-40 °C		Enable/Disable	Silicon	8-SMD Module		120 mA	LVCMOS	Surface Mount	3.3 V	1.15 mm	0.045 in	7 mm	5 mm	0.276 "	0.197 "	180 mA	200 MHz	50 MHz	Factory-Configured	25 ppm
Texas Instruments LMK61A2-156M25EVM	Timing	Board(s)	USB Powered or External Supply	SMA Connectors	LMK61A2-156M25
Texas Instruments LMK61E2-100M00EVM	Timing	Board(s)			LMK61E2-100M00
Texas Instruments LMK61E0-155M52SIAT	XO (Standard)					85 °C	-40 °C	155.52 MHz	Enable/Disable	Silicon	6-SMD Module	25 ppm	136 mA	LVPECL	Surface Mount	3.3 V	1.15 mm	0.045 in	7 mm	5 mm	0.276 "	0.197 "	208 mA
Texas Instruments LMK61E0-156M25SIAR	XO (Standard)					85 °C	-40 °C	156.25 MHz	Enable/Disable	Silicon	6-SMD Module	25 ppm	136 mA	LVPECL	Surface Mount	3.3 V	1.15 mm	0.045 in	7 mm	5 mm	0.276 "	0.197 "	208 mA
Texas Instruments LMK61E2EVM	Timing	Board(s)	Single Fractional-N PLL with VCO	Graphical User Interface (GUI)	LMK61E2																							16-Bit MCU

Catalog

155.52-MHz, LVPECL ±25 ppm, ultra-low jitter, standard differential oscillator

Key Features

• Ultra-Low Noise, High PerformanceJitter: 500-fs RMS Typical fOUT> 50 MHz on LMK61E0MLMK61E0M Supports 3.3-V LVCMOS Output up to 200 MHzTotal Frequency Tolerance of ±25 ppmSystem Level FeaturesGlitch-Less Frequency Margining: Up to ±1000 ppm From NominalInternal EEPROM: User Configurable Start-Up SettingsOther FeaturesDevice Control: Fast Mode I2C up to 1000 kHz3.3-V Operating VoltageIndustrial Temperature Range (–40ºC to +85ºC)7-mm × 5-mm 8-Pin PackageDefault Frequency: 70.656 MHzUltra-Low Noise, High PerformanceJitter: 500-fs RMS Typical fOUT> 50 MHz on LMK61E0MLMK61E0M Supports 3.3-V LVCMOS Output up to 200 MHzTotal Frequency Tolerance of ±25 ppmSystem Level FeaturesGlitch-Less Frequency Margining: Up to ±1000 ppm From NominalInternal EEPROM: User Configurable Start-Up SettingsOther FeaturesDevice Control: Fast Mode I2C up to 1000 kHz3.3-V Operating VoltageIndustrial Temperature Range (–40ºC to +85ºC)7-mm × 5-mm 8-Pin PackageDefault Frequency: 70.656 MHz

Description

The LMK61E0 family of ultra-low jitter PLLatinumTMprogrammable oscillators use fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The LMK61E0M supports 3.3-V LVCMOS outputs. The device features self start-up from on-chip EEPROM to generate a factory programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through I2C serial interface. The device provides fine and coarse frequency margining control through I2C serial interface, making it a digitally-controlled oscillator (DCXO). The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing. The LMK61E0 family of ultra-low jitter PLLatinumTMprogrammable oscillators use fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The LMK61E0M supports 3.3-V LVCMOS outputs. The device features self start-up from on-chip EEPROM to generate a factory programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through I2C serial interface. The device provides fine and coarse frequency margining control through I2C serial interface, making it a digitally-controlled oscillator (DCXO). The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.