LMK00334-Q1 Series

Automotive 4-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator

Catalog

Automotive 4-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator

Part	Type	Function	Utilized IC / Part	Supplied Contents	Input	Supplier Device Package	Mounting Type	Number of Circuits	Frequency - Max [Max]	Main Purpose	Operating Temperature [Max]	Operating Temperature [Min]	Output	Ratio - Input:Output	Voltage - Supply [Max]	Voltage - Supply [Min]	Qualification	Grade
Texas Instruments DS320-SLIMSAS-EVM	Interface	Re-Driver	LMK00334	Board(s)
Texas Instruments LMK00334RTVR					CML Crystal HCSL HSTL LVDS LVPECL SSTL	32-WQFN (5x5)	Surface Mount	1	400 MHz	PCI Express (PCIe) SATA CPU	85 °C	-40 °C	HCSL LVCMOS	3:5	3.45 V	3.15 V
Texas Instruments LMK00334RTVT					CML Crystal HCSL HSTL LVDS LVPECL SSTL	32-WQFN (5x5)	Surface Mount	1	400 MHz	PCI Express (PCIe) SATA CPU	85 °C	-40 °C	HCSL LVCMOS	3:5	3.45 V	3.15 V
Texas Instruments LMK00334RTVRQ1					CML Crystal HCSL HSTL LVDS LVPECL SSTL	32-WQFN (5x5)	Surface Mount	1	400 MHz	PCI Express (PCIe)	105 ░C	-40 °C	HCSL LVCMOS	3:5	3.45 V	3.15 V	AEC-Q100	Automotive

Catalog

Automotive 4-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator

Key Features

• AEC-Q100 Qualified for Automotive Applications:Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature RangeDevice HBM ESD Classification Level 2Device CDM ESD Classification Level C5Device MM ESD Classification Level M23:1 Input multiplexerTwo universal inputs operate up to 400 MHz and accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or single-ended clocksOne crystal input accepts a 10- to 40-MHz crystal or single-ended clockTwo banks with two differential outputs eachHCSL, or Hi-Z (selectable)Additive RMS phase jitter for PCIe Gen3/Gen4 at 100 MHz:30 fs RMS (typical)High PSRR: –72 dBc at 156.25 MHzLVCMOS output with synchronous enable inputPin-controlled configurationVCCcore supply: 3.3 V ± 5%Three independent VCCOoutput supplies: 3.3 V, 2.5 V ± 5%Industrial temperature range: –40°C to +105°C32-pin WQFN (5 mm × 5 mm)AEC-Q100 Qualified for Automotive Applications:Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature RangeDevice HBM ESD Classification Level 2Device CDM ESD Classification Level C5Device MM ESD Classification Level M23:1 Input multiplexerTwo universal inputs operate up to 400 MHz and accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or single-ended clocksOne crystal input accepts a 10- to 40-MHz crystal or single-ended clockTwo banks with two differential outputs eachHCSL, or Hi-Z (selectable)Additive RMS phase jitter for PCIe Gen3/Gen4 at 100 MHz:30 fs RMS (typical)High PSRR: –72 dBc at 156.25 MHzLVCMOS output with synchronous enable inputPin-controlled configurationVCCcore supply: 3.3 V ± 5%Three independent VCCOoutput supplies: 3.3 V, 2.5 V ± 5%Industrial temperature range: –40°C to +105°C32-pin WQFN (5 mm × 5 mm)

Description

The LMK00334 -Q1 device is a 4-output HCSL fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. It is capable of distributing the reference clock for ADCs, DACs, multi-gigabit ethernet, XAUI, fibre channel, SATA/SAS, SONET/SDH, CPRI, and high-frequency backplanes. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of two HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00334 -Q1 operates from a 3.3-V core supply and three independent 3.3-V or 2.5-V output supplies. The LMK00334 -Q1 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system. The LMK00334 -Q1 device is a 4-output HCSL fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. It is capable of distributing the reference clock for ADCs, DACs, multi-gigabit ethernet, XAUI, fibre channel, SATA/SAS, SONET/SDH, CPRI, and high-frequency backplanes. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of two HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00334 -Q1 operates from a 3.3-V core supply and three independent 3.3-V or 2.5-V output supplies. The LMK00334 -Q1 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.