AD9528 Series

JESD204B/JESD204C Clock Generator with 14 LVDS/HSTL Outputs

Catalog

JESD204B/JESD204C Clock Generator with 14 LVDS/HSTL Outputs

Part	Output	Number of Circuits	Operating Temperature [Max]	Operating Temperature [Min]	PLL	Supplier Device Package	Frequency - Max [Max]	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	Input	Package / Case	Voltage - Supply [Max]	Voltage - Supply [Min]	Divider/Multiplier	Mounting Type	Primary Attributes [custom]	Function	Utilized IC / Part	Type	Supplied Contents	Secondary Attributes
Analog Devices AD9528BCPZ	HSTL LVDS	1	85 °C	-40 °C	Yes with Bypass	72-LFCSP-VQ (10x10)	1.25 GHz	14	2	CMOS HSTL LVDS	72-VFQFN Exposed Pad CSP	3.465 V	3.135 V	Yes/No	Surface Mount
Analog Devices AD9528BCPZ-REEL7	HSTL LVDS	1	85 °C	-40 °C	Yes with Bypass	72-LFCSP-VQ (10x10)	1.25 GHz	14	2	CMOS HSTL LVDS	72-VFQFN Exposed Pad CSP	3.465 V	3.135 V	Yes/No	Surface Mount
Analog Devices AD9528/PCBZ																14-Channel	Clock Generator	AD9528	Timing	Board(s)	Graphical User Interface (GUI)

Catalog

JESD204B/JESD204C Clock Generator with 14 LVDS/HSTL Outputs

Key Features

• 14 outputs configurable for HSTL or LVDS

• Maximum output frequency6 outputs up to 1.25 GHz8 outputs up to 1 GHz

• 6 outputs up to 1.25 GHz

• 8 outputs up to 1 GHz

• Dependent on the voltage controlled crystal oscillator (VCXO) frequency accuracy (start-up frequency accuracy: <±100 ppm)

• Dedicated 8-bit dividers on each outputCoarse delay: 63 steps at 1/2 the period of the RF VCO divider output frequency with no jitter impactFine delay: 15 steps of 31 ps resolution

• Coarse delay: 63 steps at 1/2 the period of the RF VCO divider output frequency with no jitter impact

• Fine delay: 15 steps of 31 ps resolution

• Typical output to output skew: 20 ps

• Duty cycle correction for odd divider settings

• Output 12 and Output 13, VCXO output at power-up

• Absolute output jitter: <160 fs at 122.88 MHz, 12 kHz to 20 MHz integration range

• Digital frequency lock detect

• SPI- and I2C-compatible serial control port

• Dual PLL architecturePLL1Provides reference input clock cleanup with external VCXOPhase detector rate up to 110 MHzRedundant reference inputsAutomatic and manual reference switchover modesRevertive and nonrevertive switchingLoss of reference detection with holdover modeLow noise LVDS/HSTL outputs from VCXO used for radio frequency/intermediate frequency (RF/IF) synthesizersPLL2Phase detector rate of up to 275 MHzIntegrated low noise VCO

• PLL1Provides reference input clock cleanup with external VCXOPhase detector rate up to 110 MHzRedundant reference inputsAutomatic and manual reference switchover modesRevertive and nonrevertive switchingLoss of reference detection with holdover modeLow noise LVDS/HSTL outputs from VCXO used for radio frequency/intermediate frequency (RF/IF) synthesizers

• Provides reference input clock cleanup with external VCXO

• Phase detector rate up to 110 MHz

• Redundant reference inputs

• Automatic and manual reference switchover modesRevertive and nonrevertive switching

• Revertive and nonrevertive switching

• Loss of reference detection with holdover mode

• Low noise LVDS/HSTL outputs from VCXO used for radio frequency/intermediate frequency (RF/IF) synthesizers

• PLL2Phase detector rate of up to 275 MHzIntegrated low noise VCO

• Phase detector rate of up to 275 MHz

• Integrated low noise VCO

Description

The AD9528 is a two-stage PLL with an integrated JESD204B/JESD204C SYSREF generator for multiple device synchronization. The first stage phase-locked loop (PLL) (PLL1) provides input reference conditioning by reducing the jitter present on a system clock. The second stage PLL (PLL2) provides high frequency clocks that achieve low integrated jitter as well as low broadband noise from the clock output drivers. The external VCXO provides the low noise reference required by PLL2 to achieve the restrictive phase noise and jitter requirements necessary to achieve acceptable performance. The on-chip VCO tunes from 3.450 GHz to 4.025 GHz. The integrated SYSREF generator outputs single shot, N-shot, or continuous signals synchronous to the PLL1 and PLL2 outputs to time align multiple devices.The AD9528 generates six outputs (Output 0 to Output 3, Output 12, and Output 13) with a maximum frequency of 1.25 GHz, and eight outputs with a maximum frequency of up to 1 GHz. Each output can be configured to output directly from PLL1, PLL2, or the internal SYSREF generator. Each of the 14 output channels contains a divider with coarse digital phase adjustment and an analog fine phase delay block that allows complete flexibility in timing alignment across all 14 outputs. The AD9528 can also be used as a dual input flexible buffer to distribute 14 device clock and/or SYSREF signals. At power-up, the AD9528 sends the VCXO signal directly to Output 12 and Output 13 to serve as the power-up ready clocks.ApplicationsHigh performance wireless transceiversLTE and multicarrier GSM base stationsWireless and broadband infrastructureMedical instrumentationClocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs; supports JESD204B/JESD204CLow jitter, low phase noise clock distributionATE and high performance instrumentation